ISL28533 Datasheet, PDF (26/30 Pages) Intersil Corporation – 5V, Rail-Rail I/O, Zero-Drift, Programmable Gain Instrumentation Amplifiers

ISL28533, ISL28534, ISL28535, ISL28633, ISL28634, ISL28635
used for measuring the input common mode voltage for sensor
feedback and health monitoring. The differential gain stage
output pins VA+ and VA- buffers the input common mode voltage
while amplifying differential voltage. By tying two resistor across
VA+ and VA-, the buffered input common mode voltage is
extracted at the midpoint of the resistors (see Figure 74). This
voltage can be sent to an ADC for sensor monitoring or feedback
control, improving the precision and accuracy of the sensor.
V_CM
+
-
-V_DM
2
Vx
+V_DM
2
10kΩ
10kΩ
INA-
VA-
VA+
INA+
+
A1
-
R_G
R_G
-
A2
+
VA+ = Vcm + Vdm/2
VA- = Vcm - Vdm/2
Vx = [(VA+) + (VA-)] / 2
Vx = Vcm
FIGURE 74. COMMON MODE SENSING WITH VA+/VA- PINS
PROGRAMMABLE GAIN LOGIC
The ISL2853x and ISL2863x feature a three-state logic interface
for digital programming of the amplifier gain. This allows the
PGIA’s gain to be changed without an external gain setting
resistors, improving the gain accuracy and reducing component
count.
The three-state logic pins have voltage levels for recognizing valid
logic states to set the gain of the amplifier (see Figure 75). With
three logic states per input, this allows nine gain settings with
just two digital input pins (see Table 2).
V+
VIH_1_MIN
VIH_Z_MAX
VOC_H
VOC_L
VIL_Z_MIN
Logic “1”
Undefined
Logic “Z”
Undefined
VIH_1_MIN
Min High Input for Logic “1”
VIH_Z_MAX
Max Input for Logic “Z”
VOC = Floating Pin Voltage
Established by Internal Resistors
VIL_Z_MIN
Min Input for Logic “Z”
VIL_0_MAX
V-
Logic “0”
VIL_0_MAX
Max Low Input for Logic “0”
FIGURE 75. G0/G1 LOGIC THRESHOLD LEVELS
Logic states of the G0/G1 pins can be achieved by simple pin-
strapping to the supply rails for logic HI/LOW, or may be left
floating for logic Z. Internal resistors on the G0/G1 pins set the
logic level to mid-supply for logic Z. Alternatively a
micro-controller can be used to drive the pins HI/LOW or they
may be left in a High-Z state. The V_IH,V_IL, and logic Z threshold
levels are TTL/CMOS compatible for single 5V and 3V supplies.
See Table 1 for logic threshold levels.
It is important to note that logic threshold levels are referenced
to the V- negative supply rail of the amplifier. For dual supply
operation of the instrumentation amplifier logic threshold levels
are shifted by the magnitude of V-. Externally driven logic signals
require level shifting to properly set amplifier gain.
G0/G1
TABLE 1. LOGIC THRESHOLD VALUES
THRESHOLD
PARAMETER VOLTAGE
+5VDC
+3VDC
1
VIH_1_MIN
VIH_Z_MAX
VOC_H
Z
VOC_L
VIL_Z_MIN
0
VIL_0_MAX
Vs = (V+) - (V-)
0.8*Vs
0.6*Vs
0.55*Vs
0.45*Vs
0.4*Vs
0.2*Vs
4V
3V
2.75V
2.5V
2V
1V
2.4V
1.8V
1.65V
1.35V
1.2V
0.6V
TABLE 2. PROGRAMMABLE GAIN SETTINGS
GAIN (V/V)
G1
G0
ISL28533
ISL28534
ISL28535
ISL28633
ISL28634
ISL28635
0
0
1
1
1
0
Z
2
2
100
0
1
4
10
120
Z
0
5
50
150
Z
Z
10
100
180
Z
1
20
200
200
1
0
40
300
300
1
Z
50
500
500
1
1
100
1000
1000
GAIN SETTING WITH DCP
For applications without a tri-state driver the alternative solution
for programmable switching the 9 gain settings is to use a DCP.
Using a Dual DCP implements the capability to select all 9 gains
with an I²C/SPI bus interface, saving valuable GPIO lines. The
ISL23328 is a Dual 128 tap DCP that can switch the G0 and G1
pins with an I²C interface (see Figure 76). The wiper of the DCP
can be swept from V+ to V- in 128 steps.
V+
V+
SCL
SDA
I²C Bus
DUAL128 Tap
DCP
ISL23328
RHx
RW_0
RW_1
RLx
V-
G0
G1
ISL2853X
IN+ ^ISL2863X
IN-
OUT+
REF
OUT-
V-
FIGURE 76. GAIN SWITCHING WITH ISL23328 DCP
26
FN8364.0
September 24, 2013