HSMC-DVI Datasheet, PDF (26/27 Pages) List of Unclassifed Manufacturers – Terasic HSMC-DVI Daughter Board User Manual

Demonstration
The display resolution and pixel rate will change when the mode changes. In this module, the ALTERA
PLL-RECONFIG controller is used to generate various pixel rates. The RECONFIG data for various clocks
are stored on the ROM. The module source code is located in “vpg” sub-folder. For more information about
Stratix III re-configuration PLL, please refer to www.altera.com/literature/an/an454.pdf
The “Video Latch” module is used to latch DVI-RX video for high-speed video streaming.
The “Video Source Selector” module corresponds to the selected desired video source for final video display.
Altera LPM_MUX controller is used to achieve high-speed video streaming selection.
The “I2C EEPROM Write” module corresponds to writing aspects of the EDID content to EDID. For writing
custom EDID data, users can change this module.
4.7 4.6 Source Code Location
Table 4.6 shows the source code location for the DVI reference design for various FPGA main boards.
Table 4.6
FPGA Main Boards
DE3-340 Device (Port C)
DE3-150 Device (Port C)
Cyclone III Starter Board
Cyclone III Development Board (Port B)
Stratix III Development Board (Port B)
Reference design location
\Examples\DVI_Demo_DE3_340_PortC
\Examples\DVI_Demo_DE3_150_PortC
\Examples\DVI_Demo_QB3
\Examples\DVI_Demo_C3H_PortB
\Examples\DVI_Demo_S3H_PortB
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