MC3216 Datasheet, PDF (25/47 Pages) List of Unclassifed Manufacturers – Axis Accelerometer

MC3216 3-Axis Accelerometer
Preliminary Datasheet
10.4 WATCHDOG TIMER
When enabled (see MODE: Mode Control Register), the I2C watchdog timer prevents bus stall
conditions in cases where the master does not provide enough clocks to the slave to complete
a read cycle.
During a read cycle, the slave that is actively driving the bus (SDA pin) will not release the bus
until 9 SCL clock edges are detected. While the SDA pin is held low by a slave open-drain
output, any other I2C devices attached to the sample bus will be unable to communicate. If the
slave does not see 9 SCL clocks from the master within the timeout period, the slave will
assume a system problem has occurred and so the I2C circuitry will be reset, the SDA pin
released and the sensor made ready for additional I2C commands.
No other changes to registers are made.
When enabled, the I2C watchdog timer does not resolve why the master did not provide
enough clocks to complete a read cycle, but it does prevent a slave from holding the bus
indefinitely.
When enabled, the timeout period is about 200mSec.
When an I2C watchdog timer event is triggered, the I2C_WDT bit in register will be set active
by the Watchdog timer hardware. External software can detect this status by noticing this bit is
active. The act of reading register 0x04 will clears the status.
mCube Proprietary.
APS-048-0030v1.3
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