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P0040 Datasheet, PDF (22/25 Pages) List of Unclassifed Manufacturers – Terasic SFP HSMC Board User Manual | |||
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Demonstration
4.4 4.4 Demo Operation
This section describes the procedures of running the demonstration
FPGA Configuration
Demonstration Setup, File Locations, and Instructions
Transceiver Loopback Test Demo:
ï· Project directory: sfp_hsmb_s4gx_pcie_xcvr_loopback_6p25Gbps_restored
ï· Bit Stream used: hsmc_loopback.sof
ï· SFP HSMC Setup
ï¼ Insert SFP modules with loopback connectors into SFP ports 0-3 on the SFP HSMC board
ï¼ Set SW5 switches on the SFP HSMC all to the â0â position
ï· Stratix IV GX FPGA Development Kit Setup
ï¼ Set SW3 switches 1-3 & 5-8 in the âdownâ position.
ï¼ Set SW3 switch 4 in the âupâ position
ï¼ Set SW4 switches 1,2,4 in the âupâ position and switches 3,5,6,8 in the âdownâ position
ï¼ Set the rotary switch (SW2) to the 0 position
ï· Power on the Stratix IV GX FPGA Development Board and download the SOF file
(hsmc_loopback.sof)
ï· Press and release CPU reset button located on the host board to initiate the test
ï· Press and release PB0, enabling comma detect
ï· Press and release PB1 enabling channel bonding
ï· Press and release PB2, start transmitting PRBS data
ï· LED0, LED1, and LED2 should be ON and LED3 should be OFF.
ï· Remove one of the SFP modules or one side of a connector so that the loopback will fail. A Failure
is indicated on the Stratix IV GX FPGA Dev Kit when LED3 turns ON
ï· To reset the board test system, press and release the CPU reset button on the host board
ï· Press and release PB1 and PB2 at the same time creates an error in the transmitter data stream,
where LED3 should be ON
ï· Press and release, the CPU reset button on the host board and verify the results
LVDS Loopback Test Demo:
ï· Project directory: sfp_hsmb_s4gx_pcie_lvds_loopback_restored
ï· Bit Stream used: hsmc_loopback.sof
ï· SFP HSMC Setup
ï¼ Insert SFP modules with loopback connectors into SFP ports 4-7 on the SFP HSMC board
ï¼ Set SW4 switches on the SFP HSMC all to the â1â position
ï· Stratix IV GX FPGA Development Kit Setup
ï¼ Set SW3 switches 1-4 & 6-8 in the âdownâ position.
ï¼ Set SW3 switch 5 in the âupâ position
ï¼ Set SW4 switches 1,2,4 in the âupâ position and switches 3,5,6,8 in the âdownâ position
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