ML22Q563-NNNMB Datasheet, PDF (21/66 Pages) List of Unclassifed Manufacturers – 4-Channel Mixing Speech Synthesis LSI

FEDL2256X-06
ML22Q563/ML2256X
FUNCTIONAL DESCRIPTION
Synchronous Serial Interface
The CSB, SCK, SI, and SO pins are used to input various commands or read the status of the device.
For command input, after inputting a “L” level to the CSB pin, input data through the SI pin with MSB first in
sync with the SCK clock signal. The data input through the SI pin is shifted into the LSI in sync with the SCK
clock signal, then the command is executed at the eighth pulse of the rising or falling edge of the SCK clock.
For status reading, after a “L” level is input to the CSB pin, stauts is output from the SO pin in sync with the
SCK clock signal.
Choosing between rising edges and falling edges of the clock pulses input through the SCK pin is determined by
the signal input through the DIPH pin:
- When the DIPH pin is at a “L” level, the data input through the SI pin is shifted into the LSI on the rising edges
of the SCK clock pulses and a status signal is output from the SO pin on the falling edges of the SCK clock
pulses.
- When the DIPH pin is at a “H” level, the data input through the SI pin is shifted into the LSI on the falling
edges of the SCK clock pulses and a status signal is output from the SO pin on the rising edges of the SCK clock
pulses.
It is possible to input commands even with the CSB pin tied to a “L” level. However, if unexpected pulses
caused by noise etc. are induced through the SCK pin, SCK clock pulses are incorrectly counted, causing a
failure in normal input of command. In addition, the serial interface can be brought back to its initial state by
driving the CSB pin at a “H” level.
When the CSB pin is at ta “L” level, the status of each channel is output serially in sync with the SCK clock.
When the CSB pin is at a ”H” level, the SO pin goes into a high impedance state.
• C om ma nd In pu t Timi ng : SCK r isin g e dge ope ra tion (wh e n D IPH p in = “L” le vel )
C SB
SCK
SI
D 7 D6 D5 D4 D3 D 2 D 1 D0
(MSB)
(LSB )
• C om ma nd In pu t Timi ng : SCK fa lling edg e o pe ra tio n (whe n DIPH pin = “H” le vel )
C SB
SCK
SI
D 7 D6 D5 D4 D3 D 2 D 1 D0
(MSB)
(LSB )
• C om ma nd O u tpu t T imi ng : SC K fa llin g ed g e o pe ra tio n (w he n D IPH pin = “L ” le ve l)
C SB
SCK
SO
(MSB)
(LSB )
D 7 D6 D5 D4 D3 D 2 D 1 D0
Co m ma nd O utp ut Tim in g: S CK ris ing ed g e op era tio n ( wh en DIPH pi n = “H ” le vel )
C SB
SCK
SO
(MSB)
(LSB )
D 7 D6 D5 D4 D3 D 2 D 1 D0
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