AT25DN512C Datasheet, PDF (21/40 Pages) List of Unclassifed Manufacturers – 512-Kbit, 2.3V Minimum SPI Serial Flash Memory with Dual-I/O Support

Figure 11-2. Write Status Register
CS
SCK
SI
SO
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
OPC ODE
STATUS REGISTER IN
0 0 0 0 0 0 0 1DXXXXDXX
MSB
MSB
HIGH-IMPEDANCE
11.3
Write Status Register Byte 2
The Write Status Register Byte 2 command is used to modify the RSTE. Using the Write Status Register Byte 2
command is the only way to modify the RSTE in the Status Register during normal device operation. Before the Write
Status Register Byte 2 command can be issued, the Write Enable command must have been previously issued to set the
WEL bit in the Status Register to a Logical 1.
To issue the Write Status Register Byte 2 command, the CS pin must first be asserted and then the opcode 31h must be
clocked into the device followed by one byte of data. The one byte of data consists of three don’t-care bits, the RSTE bit
value, and four additional don’t-care bits (see Table 11-4). Any additional data bytes sent to the device will be ignored.
When the CS pin is deasserted, the RSTE bit in the Status Register will be modified, and the WEL bit in the Status
Register will be reset back to a Logical 0.
The complete one byte of data must be clocked into the device before the CS pin is deasserted, and the CS pin must be
deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the operation, the state of
the RSTE bit will not change, and the WEL bit in the Status Register will be reset back to the Logical 0 state.
Table 11-4. Write Status Register Byte 2 Format
Bit 7
Bit 6
Bit 5
X
X
X
Bit 4
RSTE
Bit 3
X
Bit 2
X
Bit 1
X
Bit 0
X
Figure 11-3. Write Status Register Byte 2
CS
SCK
SI
SO
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Opcode
Status Register In
Byte 2
0 0 1 1 0 0 0 1XXXDXXXX
MSB
MSB
High-impedance
AT25DN512C 21
DS-25DN512C–037A–1/2014