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LM3S310 Datasheet, PDF (20/342 Pages) List of Unclassifed Manufacturers – Microcontroller | |||
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Architectural Overview
⢠User-enabled stalling in periodic and one-shot mode when the controller asserts the
CPU Halt flag during debug
â 16-bit Timer modes:
⢠General-purpose timer function with an 8-bit prescaler
⢠Programmable one-shot timer
⢠Programmable periodic timer
⢠User-enabled stalling when the controller asserts CPU Halt flag during debug
â 16-bit Input Capture modes:
⢠Input edge count capture
⢠Input edge time capture
â 16-bit PWM mode:
⢠Simple PWM mode with software-programmable output inversion of the PWM signal
 ARM FiRM-compliant Watchdog Timer
â 32-bit down counter with a programmable load register
â Separate watchdog clock with an enable
â Programmable interrupt generation logic with interrupt masking
â Lock register protection from runaway software
â Reset generation logic with an enable/disable
â User-enabled stalling when the controller asserts the CPU Halt flag during debug
 Synchronous Serial Interface (SSI)
â Master or slave operation
â Programmable clock bit rate and prescale
â Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep
â Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
â Programmable data frame size from 4 to 16 bits
â Internal loopback test mode for diagnostic/debug testing
 UART
â Two fully programmable 16C550-type UARTs
â Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs to reduce CPU interrupt
service loading
â Programmable baud-rate generator with fractional divider
â Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
â FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
â Standard asynchronous communication bits for start, stop, and parity
â False-start-bit detection
â Line-break generation and detection
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October 6, 2006
Preliminary
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