KAD5510P-50 Datasheet, PDF (20/28 Pages) List of Unclassifed Manufacturers – 10-Bit, 500MSPS A/D Converter

KAD5510P-50
Figure 41. Instruction/Address Phase
Figure 42. 2-Byte Transfer
Figure 43. N-Byte Transfer
[W1:W0]
00
01
10
11
Bytes Transferred
1
2
3
4 or more
Table 6. Byte Transfer Selection
Figures 42 and 43 illustrate the timing relationships for
2-byte and N-byte transfers, respectively. The opera-
tion for a 3-byte transfer can be inferred from these
diagrams.
SPI Configuration
Address 0x00: chip_port_config
Bit ordering and SPI reset are controlled by this regis-
ter. Bit order can be selected as MSB to LSB (MSB first)
or LSB to MSB (LSB first) to accommodate various mi-
crocontrollers.
Bit 7 SDO Active
Bit 6 LSB First
Setting this bit high configures the SPI to inter-
pret serial data as arriving in LSB to MSB order.
Bit 5 Soft Reset
Rev 0.5.1 Preliminary
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