SGP04G72A1BD1SA-DCRT Datasheet, PDF (2/17 Pages) List of Unclassifed Manufacturers – 4GB DDR3 –Registered ECC RDIMM

Preliminary Data Sheet
Rev.0.9 16.01.2014
This Swissbit module is an industry standard 240-pin 8-byte DDR3 registered SDRAM Dual-In-line Memory
Module (RDIMM) which is organized as x72 high speed CMOS memory arrays. The module uses internally
configured octal-bank DDR3 SDRAM devices. The module uses double data rate architecture to achieve high-
speed operation. DDR3 SDRAM modules operate from a differential clock (CK and CK#). READ and WRITE
accesses to a DDR3 SDRAM module is burst-oriented; accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence. The burst length is either four or eight locations. An
auto precharge function can be enabled to provide a self-timed row precharge that is initiated at the end of a burst
access. The DDR3 SDRAM devices have a multibank architecture which allows a concurrent operation that is
providing a high effective bandwidth. A self refresh mode is provided and a power-saving “power-down” mode. All
inputs and all full drive-strength outputs are SSTL_15 compatible.
The DDR3 SDRAM module uses the serial presence detect (SPD) function implemented via serial EEPROM
using the standard I²C protocol. This nonvolatile storage device contains 256 bytes. The first 128 bytes are
utilized by the DIMM manufacturer (Swissbit) to identify the module type, the module’s organization and several
timing parameters. The second 128 bytes are available to the end user.
Module Configuration
Organization
512M x 72bit
DDR3 SDRAMs used
9 x 512M x 8bit (4Gbit)
Row
Addr.
16
Device Bank
Addr.
BA0, BA1, BA2
Column.
Addr.
10
Refresh
Module
Bank Select
8k
S0#
Module Dimensions
in mm
133.35 (long) x 30 (high) x 4.0 [max] (thickness)
Timing Parameters
Part Number
SGP04G72A1BD1SA-DCRT
Module
Density
4 GByte
Transfer Rate
12.8 GB/s
Clock Cycle/Data bit rate
1.25ns/1600MT/s
Latency
11-11-11
Pin Name
A0 – A9, A11, A13 – A15
A10/AP
A12/BC
BA0 – BA2
DQ0 – DQ63
CB0 – CB7
DQS0 – DQS8
DQS0# – DQS8#
TDQS9-17, TDQS9-17#
S0#
RAS#
CAS#
WE#
CKE0
CK0 – CK1
Address Inputs (A15 not functional, but included in parity check)
Address Input / Auto precharge Bit
Address Input / Burst chop
Bank Address Inputs
Data Input / Output
Data check bits Input / Output
Data Strobe, positive line
Data Strobe, negative line (only used when differential data strobe mode is enabled)
Redundant data strobe (x8 devices only): When TDQS is enabled via EMRS, DM is disabled
and TDQS / TDQS# provide termination resistance for x4 based modules
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Clock Enable
Clock Inputs, positive line
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: [phone]
Fax: [phone]
www.swissbit.com
eMail: [e-mail]
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