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P1402CDG Datasheet, PDF (2/5 Pages) List of Unclassifed Manufacturers – N-Channel Logic Level Enhancement Mode Field Effect Transistor
NIKO-SEM
N-Channel Logic Level Enhancement
Mode Field Effect Transistor
P1402CDG
TO-252 (DPAK)
Lead-Free
DYNAMIC
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge2
Gate-Source Charge2
Gate-Drain Charge2
Turn-On Delay Time2
Rise Time2
Turn-Off Delay Time2
Fall Time2
Ciss
Coss
Crss
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
VGS = 0V, VDS = 15V, f = 1MHz
VDS = 0.5V(BR)DSS, VGS = 5V,
ID = 18A
VDS = 10V,
ID ≅ 18A, VGS = 5V, RGS = 3.3Ƹ
SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TC = 25 °C)
Continuous Current
Pulsed Current3
Forward Voltage1
IS
ISM
VSD
IF = IS, VGS = 0V
Reverse Recovery Time
trr
Peak Reverse Recovery Current
IRM(REC)
IF = IS, dlF/dt = 100A / µS
Reverse Recovery Charge
Qrr
1Pulse test : Pulse Width ≤ 300 µsec, Duty Cycle ≤ 2Ĉ.
2Independent of operating temperature.
3Pulse width limited by maximum junction temperature.
500
310
pF
125
17
1.5
nC
10.5
7.5
83
nS
18
23
45
A
140
1.3 V
37
nS
200
A
0.043
µC
REMARK: THE PRODUCT MARKED WITH “P1402CDG”, DATE CODE or LOT #
Orders for parts with Lead-Free plating can be placed using the PXXXXXXG parts name.
2
NOV-05-2004