C8051 Datasheet, PDF (2/3 Pages) List of Unclassifed Manufacturers – Legacy-Speed 8-Bit Processor Core

Functional Description
The C8051 is partitioned into modules described below:
Memory Control Unit
• Can address up to 64K bytes of External Program
Memory Space
• Can address up to 64K bytes of External Data Memory
Space
Core Engine
The C8051 engine is composed of four components:
• Control unit
• Arithmetic-logic unit
• Memory control unit
• RAM and SFR control unit
The C8051 engine allows fetching instructions from pro-
gram memory and execution using RAM or SFR.
Control Unit
The Control Unit performs instruction fetch and execution
from the Memory Control Unit and the RAM_SFR Control
Unit.
RAM and SFR Unit
• Can Address up to 256 bytes of Read/Write Data Mem-
ory space
• Serves the interface for off-core Special Function Regis-
ters
Arithmetic-logic Unit
• 8-bit arithmetic & logic operations
• Boolean manipulations
• 8 x 8-bit multiplication
• 8 / 8-bit division
Timer 0 and 1
Timers 0 and 1 are nearly identical. Timers 0 and 1 both
have four modes. They are:
• 13-bit Timer/counter
• 16-bit Timer/counter
• 8-bit timer/counter with auto reload
• two 8-bit timers
The later mode is available to Timer 0 only. Each timer can
also serve as a counter of external pulses (1 to 0 transition)
on the corresponding T0 or T1 pin. One other option is to
gate the timer/counter using an external control signal. This
allows the timer to measure the pulse width of external sig-
nals.
Serial
The C8051 core provides interface for serial communica-
tion. The serial port is capable of both synchronous and
asynchronous modes. In synchronous mode, the microcon-
troller generates the clock and operates in a half-duplex
mode. In asynchronous mode, full duplex operation is
available. Receive data is buffered in a holding register.
This allows the serial to receive an incoming word before
software has read the previous value.
The port provides four operating modes. These offer differ-
ent communication protocols and baud rates:
• Synchronous mode, fixed baud rate
• 8-bit UART mode, variable baud rate
• 9-bit UART mode, fixed baud rate
• 9-bit UART mode, variable baud rate
Interrupt Service Routine
The C8051 core improves two-priority interrupt system.
There are 5 interrupt sources. Each source has an inde-
pendent priority bit, flag, interrupt vector, and enable. In
addition, interrupts can be globally enabled or disabled.
Ports
The C8051 provides four I/O ports. Port 0 – Port 3 is an 8-
bit bi-directional I/O ports with separated inputs and out-
puts.
Port 0 is also the multiplexed low-order address and data
bus during accesses to external program and data memo-
ries.
Port 1 also serves the special features like external inter-
rupt inputs, Serial 1 interface, and Timer 2 inputs.
Port 2 emits the high-order address byte during fetches
from external program memory that use 16-bit addresses
(MOVX @DPTR).
Port 3 also serves the special features such as read and
write strobes for external data memory, Serial 0 interface,
Timer 0 and Timer 1 inputs.
Clock Control
The Clock Control unit generates the internal synchronous
reset. It also contains registers for selecting the clock for
timers.
Interface for On-Chip Instrumentation
The OCI unit serves as an interface for On-Chip Instrumen-
tation. The OCI provides the following functions for
communication with On-Chip Instrumentation:
• the run/stop control
• single-step mode
• software breakpoint
• debugger program
• hardware breakpoint
• program trace
• access to ACC register
Power Management Unit
Power Management Unit serves two power management
modes IDLE and STOP.