74HCT153PW Datasheet, PDF (2/7 Pages) List of Unclassifed Manufacturers – 74HC/HCT153 Dual 4-input multiplexer

Philips Semiconductors
Dual 4-input multiplexer
Product specification
74HC/HCT153
FEATURES
• Non-inverting output
• Separate enable for each output
• Common select inputs
• See ‘253” for 3-state version
• Permits multiplexing from n lines to
1 line
• Enable line provided for cascading
(n lines to 1 line)
• Output capability: standard
• I_CC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT153 are high-speed
Si-gate CMOS devices and are pin
compatible with low power Schottky
TTL (LSTTL). They are specified in
compliance with JEDEC standard
no. 7A.
The 74HC/HCT153 have two
identical 4-input multiplexers which
select two bits of data from up to four
sources selected by common data
select inputs (S₀, S₁). The two 4-input
multiplexer circuits have individual
active LOW output enable inputs (1E,
2E) which can be used to strobe the
outputs independently. The outputs
(1Y, 2Y) are forced LOW when the
corresponding output enable inputs
are HIGH.
The “153” is the logic implementation
of a 2-pole, 4-position switch, where
the position of the switch is
determined by the logic levels applied
to S₀ and S₁.
The logic equations for the outputs
are:
1Y = 1E.(1I₀.S₁.S₀+1I₁.S₁.S₀+
+1I₂.S₁.S₀+1I₃.S₁.S₀)
2Y = 2E.(2I₀.S₁.S₀+2I₁.S₁.S₀+
+2I₂.S₁.S₀+2I₃.S₁.S₀)
The “153” can be used to move data
to a common output bus from a group
of registers. The state of the select
inputs would determine the particular
register from which the data came. An
alternative application is a function
generator. The device can generate
two functions or three variables. This
is useful for implementing highly
irregular random logic.
The “153” is similar to the “253” but
has standard outputs.
QUICK REFERENCE DATA
GND = 0 V; T_amb = 25 °C; t_r = t_f = 6 ns
SYMBOL PARAMETER
CONDITIONS
TYPICAL
HC
HCT
t_PHL/ t_PLH
propagation delay
1I_n, 2I_n to nY
S_n to nY
nE to nY
C_L = 15 pF; V_CC = 5 V
14
16
15
17
10
11
C_I
input capacitance
3.5
3.5
C_PD
power dissipation capacitance per multiplexer notes 1 and 2
30
30
UNIT
ns
ns
ns
pF
pF
Notes
1. C_PD is used to determine the dynamic power dissipation (P_D in µW):
P_D = C_PD × V_CC2 × f_i + ∑ (C_L × V_CC2 × f_o) where:
f_i = input frequency in MHz
f_o = output frequency in MHz
C_L = output load capacitance in pF
V_CC = supply voltage in V
∑ (C_L × V_CC2 × f_o) = sum of outputs
2. For HC the condition is V_I = GND to V_CC
For HCT the condition is V_I = GND to V_CC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic
Package Information”.
December 1990
2