MC3253 Datasheet, PDF (19/72 Pages) List of Unclassifed Manufacturers – Axis Accelerometer

MC3253 3-Axis Accelerometer
Preliminary Datasheet
8 INTERRUPTS
The sensor device utilizes output pin INTN to signal to an external microprocessor that an
event has been sensed. The microprocessor would contain an interrupt service routine which
would perform certain tasks after receiving this interrupt and reading the associated status bits,
perhaps after the product was put into a certain orientation or had been tapped. The
microprocessor would set up the registers in the sensor so that when a specific event is
detected, the microprocessor would receive the interrupt and the interrupt service routine
would be executed.
For products that will instead use polling, the method of reading sensor data would be slightly
different. Instead of receiving an interrupt when an event occurs, the microprocessor must
periodically poll the sensor and read status data while the INTN pin is not used. For most
applications this is likely best done at the sensor sampling rate or faster. Note that at least one
I2C STOP condition must be present between samples in order for the sensor to update the
sample data registers.
In this case, the event detection bits (TAPD, SHAKED, DROPD) and associated interrupt
enable bits in the TILT: Status Register must still be set up as if interrupts would occur
in order for the status registers to be updated with proper data.
Although the INTN is not connected, the registers in the sensor will still contain valid status and
so can be used by software to know the orientation of the product or if an event has occurred.
8.1 ENABLING AND CLEARING INTERRUPTS
The INTEN: Interrupt Enable Register determines which events generate interrupts. When an
event is detected, it is masked with an interrupt enable bit in this register and the
corresponding status bit is set in the TILT: Status Register. Multiple interrupt events might be
reported at the same time in the TILT: Status Register, so software must interpret and prioritize
the results.
The pin INTN is cleared during the next I2C bus cycle after the device ID has been
recognized by the device.
When an interrupt is triggered, the first I2C read access to the device clears INTN pin. The
condition (TAPD, SHAKED, DROPD) that generated the interrupt will remain held in the TILT:
Status Register until it is read. Note that the orientation bit-fields POLA and BAFR are
continuously updated (every sample) in the TILT: Status Register and are not held. Note that
multiple interrupts may be active at the same time, and so a software routine reading the TILT:
Status Register should account for this.
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APS-048-0026v1.2
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