SI4420-D1-FT Datasheet, PDF (17/33 Pages) List of Unclassifed Manufacturers – Si4420 Universal ISM Band FSK Transceiver

Si4420
Bits 2-0 (f2 to f0): DQD threshold parameter.
Note: To let the DQD report "good signal quality" the threshold parameter should be less than 4 in the case when the bitrate is
close to the deviation. At higher deviation/bitrate settings higher threshold parameter can report "good signal quality" as
well.
7. FIFO and Reset Mode Command
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 0 1 0 f3 f2 f1 f0 0 al ff dr
POR
CA80h
Bits 7-4 (f3 to f0): FIFO IT level. The FIFO generates IT when the number of received data bits reaches this level.
Bit 2 (al): Set the input of the FIFO fill start condition:
al
0
Synchron pattern
1
Always fill
Note: Synchron pattern in microcontroller mode is 2DD4h.
SYNCHRON
PATTERN
al
FFOV
ff
FFIT
ef*
er**
FIFO_LOGIC
FIFO_WRITE _EN
nFIFO_RESET
Note:
* For details see the Configuration Setting Command
** For deatils see the Power Management Command
Bit 1 (ff): FIFO fill will be enabled after synchron pattern reception. The FIFO fill stops when this bit is cleared.
Bit 0 (dr): Disables the highly sensitive RESET mode. If this bit is cleared, a 600 mV glitch in the power supply may cause a system reset. For
more detailed description see the Reset modes section.
Note: To restart the synchron pattern recognition, bit 1 should be cleared and set.
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