MS4515DO Datasheet, PDF (17/19 Pages) List of Unclassifed Manufacturers – PCB Mounted Digital Output Transducer

MS4515DO
TIMING DIAGRAM
I2C INTERFACE PRRAMETERS
PARAMETERS
SYMBOL
MIN
SCLK CLOCK FREQUENCY
START CONDITION HOLD TIME RELATIVE TO SCL EDGE
MINIMUM SCL CLOCK LOW WIDTH @1
MINIMUM SCL CLOCK HIGH WIDTH @1
START CONDITION SETUP TIME RELATIVE TO SCL EDGE
DATA HOLD TIME ON SDA RELATIVE TO SCL EDGE
DATA SETUP TIME ON SDA RELATIVE TO SCL EDGE
STOP CONDITION SETUP TIME ON SCL
BUS FREE TIME BETWEEN STOP AND START CONDITION
FSCL
100
tHDSTA
0.1
tLOW
0.6
tHIGH
0.6
tSUSTA
0.1
tHDDAT
0
tSUDAT
0.1
tSUSTO
0.1
tBUS
2
@1 COMBINED LOW AND HIGH WIDTHS MUST EQUAL OR EXCEED MINIMUM SCL PERIOD.
I²C TIMING DIAGRAM
TYP MAX UNITS
400 ^KHz
uS
uS
uS
uS
uS
uS
uS
uS
SDA
SCL
t_LOW
t _SUDAT
t_HDDAT
t_HDDAT t_HIGH
t_HDSTA
t _SUSTA
t_BUS
t _SUSTO
SPI INTERFACE PRRAMETERS
PARAMETERS
SCLK CLOCK FREQUENCY
SS DROP TO FIRST CLOCK EDGE
MINIMUM SCL CLOCK LOW WIDTH @1
MINIMUM SCL CLOCK HIGH WIDTH @1
CLOCK EDGE TO DATA TRANSITION
RISE OF SS RELATIVE TO LAST CLOCK EDGE
BUS FREE TIME BETWEEN RISE AND FALL OF SS
SYMBOL
MIN
FSCL
50
tHDSS
2.5
tLOW
0.6
tHIGH
0.6
tCLKD
0
tSUSS
0.1
tBUS
2
@1 COMBINED LOW AND HIGH WIDTHS MUST EQUAL OR EXCEED MINIMUM SCLK PERIOD.
SPI TIMING DIAGRAM
TYP MAX UNITS
800
KHz
uS
uS
uS
0.1
uS
uS
uS
SCLK
MISO ^Hiz
t_{C L K D}
SS
MS4515DO
t _LOW
t _CLKD
www.meas-spec.com
17/19
t _SUSS
Hiz
t _BUS
April 2012