LM3S628 Datasheet, PDF (160/357 Pages) List of Unclassifed Manufacturers – Microcontroller

General-Purpose Timers
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020
This register show the state of the GPTM's controller-level interrupt. If an interrupt is unmasked in
GPTMIMR, and there is an event that causes the interrupt to be asserted, the corresponding bit is
set in this register. All bits are cleared by writing a 1 to the corresponding bit in GPTMICR.
GPTM Masked Interrupt Status (GPTMMIS)
Offset 0x020
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Type
RO
Reset
0
reserved
RO
RO
RO
0
0
0
CBEMIS CBMMIS TBTOMIS
RO
RO
RO
RO
RO
0
0
0
0
0
reserved
RO
RO
0
0
RTCMIS CAEMIS CAMMIS TATOMIS
RO
RO
RO
RO
RO
0
0
0
0
0
Bit/Field
31:11
10
9
8
7:4
3
2
1
0
Name
reserved
CBEMIS
CBMMIS
TBTOMIS
reserved
RTCMIS
CAEMIS
CAMMIS
TATOMIS
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
Description
Reserved bits return an indeterminate value, and should never
be changed.
GPTM CaptureB Event Masked Interrupt
This is the CaptureB event interrupt status after masking.
GPTM CaptureB Match Masked Interrupt
This is the CaptureB match interrupt status after masking.
GPTM TimerB Time-Out Masked Interrupt
This is the TimerB time-out interrupt status after masking.
Reserved bits return an indeterminate value, and should never
be changed.
GPTM RTC Masked Interrupt
This is the RTC event interrupt status after masking.
GPTM CaptureA Event Masked Interrupt
This is the CaptureA event interrupt status after masking.
GPTM CaptureA Match Masked Interrupt
This is the CaptureA match interrupt status after masking.
GPTM TimerA Time-Out Masked Interrupt
This is the TimerA time-out interrupt status after masking.
160
October 8, 2006
Preliminary