LM3S601_06 Datasheet, PDF (152/397 Pages) List of Unclassifed Manufacturers – Microcontroller

General-Purpose Timers
Figure 9-2. 16-Bit Input Edge Count Mode Example
Count
0x000A
0x0009
0x0008
0x0007
0x0006
Timer reload
on next cycle Ignored Ignored
Timer stops,
flags
asserted
Input Signal
9.2.3.3
16-Bit Input Edge Time Mode
In Edge Time mode, the timer is configured as a free-running down-counter initialized to the value
loaded in the GPTMTnILR register (or 0xFFFF at reset). This mode allows for event capture of
both rising and falling edges. The timer is placed into Edge Time mode by setting the TnCMR bit in
the GPTMTnMR register, and the type of event that the timer captures is determined by the
TnEVENT fields of the GPTMCTL register.
When software writes the TnEN bit in the GPTMCTL register, the timer is enabled for event
capture. When the selected input event is detected, the current Tn counter value is captured in the
GPTMTnR register and is available to be read by the controller. The GPTM then asserts the
CnERIS bit (and the CnEMIS bit, if the interrupt is not masked).
After an event has been captured, the timer does not stop counting. It continues to count until the
TnEN bit is cleared. When the timer reaches the 0x0000 state, it is reloaded with the value from the
GPTMnILR register.
Figure 9-3 shows how input edge timing mode works. In the diagram, it is assumed that the start
value of the timer is the default value of 0xFFFF, and the timer is configured to capture rising edge
events.
Each time a rising edge event is detected, the current count value is loaded into the GPTMTnR
register, and is held there until another rising edge is detected (at which point the new count value
is loaded into GPTMTnR).
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October 8, 2006
Preliminary