PS20355 Datasheet, PDF (15/25 Pages) List of Unclassifed Manufacturers – Nordig Unified DVB-T COFDM

PS20355
Table 4 – Timing of 2-Wire Bus
Parameter
Values with 20.48 MHz
Values with 4MHz clock
Symbol
clock*
Unit
Min.
Max.
Min.
Max.
CLK clock frequency (Primary)
Bus free time between a STOP and START
condition.
Hold time (repeated) START condition.
LOW period of CLK clock.
HIGH period of CLK clock.
Set-up time for a repeated START condition.
Data hold time (when input).
Data set-up time
Rise time of both CLK and DATA signals.
Fall time of both CLK and DATA signals, (100pF to
ground).
Set-up time for a STOP condition.
f
CLK
t
BUFF
t
HD;STA
t
LOW
t
HIGH
t
SU;STA
t
HD;DAT
t
SU;DAT
t
R
tF
t
SU;STO
0
4.7
4.0
4.7
4.0
4.7
0
250
4.0
100
0
1.3
0.6
1.3
0.6
0.6
3.45
0
1000
100
20 + 0.1C †
b
300
20 + 0.1Cb ^†
0.6
400 kHz
µs
µs
µs
µs
µs
0.9 µs
ns
300 ns
300 ns
µs
*. Or 27.00 MHz clock
†. Cb = the total capacitance on either clock or data line in pF to maximum of 400pF.
3.2 MPEG
3.2.1 Data Output Header Format
Figure 7 - DVB Transport Packet Header Byte
188 byte packet output
184 Transport packet bytes
Transport
Packet
Header
4 bytes
0 1 0 0 0 1 1 1 1st byte
TEI
2nd byte
MDO[7]
MDO[0]
After decoding the 188-byte MPEG packet, it is output on the MDO pins in 188 consecutive clock cycles.
Additionally when the TEI_En bit in the OP_CTRL_0 register (0x5A) is set high (default), the TEI bit of any
uncorrectable packet will automatically be set to ‘1’. If TEI_En bit is low then TEI bit will not be changed (but note that if
this bit is already 1, for example, due to a channel error which has not been corrected, it will remain high at output).
PLESSEY SEMICONDUCTORS LTD
TAMERTON ROAD | ROBOROUGH | PLYMOUTH | DEVON | PL6 7BQ
15