ISD2360SYI Datasheet, PDF (15/32 Pages) List of Unclassifed Manufacturers – Digital ChipCorder with Embedded Flash 3-Channel Audio Playback

PRELIMINARY DATASHEET
SSB
T_{R / B}
SCLK
0 12 3 4 5 6 7
01234567
RDY/BSYB
=1
MISO Z
X
PD RDY INT FULL X
VG BUF
BSY FUL
CMD
BSY
MOSI
X C7 C6 C5 C4 C3 C2 C1 C0
=1
PD RDY INT FULL X
VG BUF CMD
BSY FUL BSY
D7 D6 D5 D4 D3 D2 D1 D0 X
Figure 8-2 RDY/BSYB Timing for SPI Writing Transactions.
If the SCLK does not remain high, RDY bit of the status register will be set to zero and be reported via
the MISO pin so the host can take the necessary actions (i.e., terminate SPI transmission and re-
transmit the data when the RDY/BSYB pin returns to high).
For commands (i.e., DIG_READ, SPI_PCM_READ) that read data from the ISD2360 device, MISO is
used to read the data; therefore, the host must monitor the status via the RDY/BSYB pin and take the
necessary actions. The INT pin will go low to indicate (1) data overrun/overflow when sending data to
the ISD2360; or (2) invalid data from ISD2360. See Figure 8-3 for the timing diagram.
To avoid RDY/BSYB polling for digital operations the following conditions must be met:
 Ensure device is idle (CMD_BSY=0 in status) before operation.
 Digital Write: Send 32 bytes of data or less in a digital write transaction or ensure that there is
a 24µs period between each byte sent where SCLK is held high.
 Digital Read: Ensure a 2µs period between last address byte of digital read command and first
data byte where SCLK is held high.
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Publication Release Date: 4/21/2012
Revision 0.3