M4TKLG6AE Datasheet, PDF (134/144 Pages) List of Unclassifed Manufacturers – 32-bit Microcontroller

8.7 SPI Dynamic Characteristics
8.7.1 Dynamic Characteristics of Data Input and Output Pin
SYMBOL
tW(SCKH)
tW(SCKL)
tDS
tH(MI)
tV
tH(MO)
tW(SCKH)
tW(SCKL)
tDS
tH(MI)
tV
tH(MO)
PARAMETER
MIN.
TYP.
MAX.
SPI MASTER MODE (VDD = 4.5 V~5.5V, 30 PF LOADING CAPACITOR)
SPI high and low time, peripheral clock
= 20MHz
22.5
-
27.5
Data input setup time
Data input hold time
2
-
-
4
-
-
Data output valid time
-
-
1
Data output hold time
0
-
-
SPI MASTER MODE (VDD = 3.0~3.6 V, 30 PF LOADING CAPACITOR)
SPI high and low time, peripheral clock
= 20MHz
22.5
-
27.5
Data input setup time
2
Data input hold time
4
Data output valid time
-
1
Data output hold time
0
-
-
SPI Clock
CLKPOL=0
TXNEG=1
RXNEG=0
CLKPOL=1
TXNEG=0
RXNEG=1
SPI data output
(SPI_MOSI)
SPI data input
(SPI_MISO)
t_V
tr(SCK) tf(SCK)
Data Valid
t_DS
t_DH
Data Valid
Data Valid
Data Valid
SPI Clock
CLKPOL=0
TXNEG=0
RXNEG=1
CLKPOL=1
TXNEG=1
RXNEG=0
SPI data output
(SPI_MOSI)
SPI data input
(SPI_MISO)
t_V
Data Valid
t_DS
t_DH
Data Valid
Data Valid
Data Valid
Figure 8.7-1 SPI Master Mode Timing Diagram
Jan. 06, 2016
Page 134 of 144
M4TK
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev.1.00