TS30022 Datasheet, PDF (13/19 Pages) List of Unclassifed Manufacturers – High Efficiency 1A/2A/3A Current-Mode Synchronous Buck DC/DC Converter, 2MHz and 470mA LDO

TS30021/22/23
Version 1.5
TYPICAL APPLICATION SCHEMATIC
Adjustable Switcher Output
VCC
Cbypass
VCC
V_LDO
Cbypass-LDO
V_LDO
EN
EN
BST
VSW
FB_SW
VO_LDO
FB_LDO
PG
CBST
Lout
RTOPSW
RBOTSW
VOUT
Cout
RTOP
RBOT
Cout_LDO
VOUT
10kW
(Optional)
VOUT_LDO
PG
Figure 22: TS30021/22/23 Application Schematic
A minimal schematic suitable for most applications is shown on page 1. Figure 22 includes optional
components that may be considered to address specific issues as listed in the External Component
Selection section.
PCB LAYOUT
For proper operation and minimum EMI, care must be taken during PCB layout. An improper layout can lead to issues such as
poor stability and regulation, noise sensitivity and increased EMI radiation. The main guidelines are the following:
 provide low inductive and resistive paths for loops with high di/dt,
 provide low capacitive paths with respect to all the other nodes for traces with high di/dt,
 sensitive nodes not assigned to power transmission should be referenced to the analog signal ground (GND) and be
always separated from the power ground (PGND).
The negative ends of CBYPASS, COUT and the Schottky diode DCATCH (optional) should be placed close to each other and connected
using a wide trace. Vias must be used to connect the PGND node to the ground plane. The PGND node must be placed as close as
possible to the TS30021/22/23 PGND pins to avoid additional voltage drop in traces.
The bypass capacitor CBYPASS (optionally paralleled to a 0.1µF capacitor) must be placed close to the VCC pins of
TS30021/22/23.
The inductor must be placed close to the VSW pins and connected directly to COUT in order to minimize the area between the
VSW pin, the inductor, the COUT capacitor and the PGND pins. The trace area and length of the switching nodes VSW and BST
should be minimized.
For the adjustable output voltage version of the TS30021/22/23, feedback resistors RBOTSW and RTOPSW are required for Vout
settings greater than 0.8V and should be placed close to the TS30021/22/23 in order to keep the traces of the sensitive node FB
as short as possible and away from switching signals. RBOTSW should be connected to the analog ground pin (GND) directly and
should never be connected to the ground plane. The analog ground trace (GND) should be connected in only one point to the
power ground (PGND). A good connection point is under the TS30021/22/23 package to the exposed thermal pad and vias
which are connected to PGND. RTOPSW will be connected to the VOUT node using a trace that ends close to the actual load.
Specifications subject to change
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