EFM32GG332F512 Datasheet, PDF (13/67 Pages) List of Unclassifed Manufacturers – High Performance 32-bit processor @ up to 48 MHz

Preliminary
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3.5 Transition between Energy Modes
Table 3.5. Energy Modes Transitions
Symbol
t_EM10
Parameter
Transition time from EM1 to EM0
t_EM20
Transition time from EM2 to EM0
t_EM30
Transition time from EM3 to EM0
t_EM40
Transition time from EM4 to EM0
1_{Core wakeup time only.}
3.6 Power Management
Min
Typ Max Unit
0¹
HF
core
CLK
cycles
2
µs
2
µs
163
µs
The EFM32GG requires the AVDD_x, VDD_DREG and IOVDD_x pins to be connected together at the
PCB level. For practical schematic recommendations, please see the application note, "AN0002 EFM32
Hardware Design Considerations".
Table 3.6. Power Management
Symbol
V_BODextthr-
V_BODintthr-
V_BODextthr+
V_PORthr+
t_RESET
C_DECOUPLE
C_{USB_VREGO}
C_{USB_VREGI}
Parameter
Condition
Min
Typ
Max
Unit
BOD threshold on falling
external supply voltage
1.82
1.85 V
BOD threshold on falling
internally regulated supply
voltage
1.62
1.68 V
BOD threshold on rising ex-
ternal supply voltage
1.85
V
Power-on Reset (POR)
threshold on rising external
supply voltage
1.98 V
Delay from reset is re-
Applies to Power-on Reset,
leased until program execu- Brown-out Reset and pin re-
tion starts
set.
163
µs
Voltage regulator decou-
pling capacitor.
X5R capacitor recommended.
Apply between DECOUPLE
pin and GROUND
1
µF
USB voltage regulator out
decoupling capacitor.
X5R capacitor recommended.
Apply between USB_VREGO
pin and GROUND
1
µF
USB voltage regulator in
decoupling capacitor.
X5R capacitor recommended.
Apply between USB_VREGI
pin and GROUND
4.7
µF
2013-06-28 - EFM32GG332FXX - d0126_Rev1.10
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