N76E003 Datasheet, PDF (121/267 Pages) List of Unclassifed Manufacturers – Microcontroller

N76E003 Datasheet
SCON_1 – Serial Port 1 Control (bit-addressable)
7
6
5
4
SM0_1/FE_1 SM1_1
SM2_1
REN_1
R/W
R/W
R/W
R/W
Address: F8H
3
TB8_1
R/W
2
RB8_1
R/W
1
0
TI_1
RI_1
R/W
R/W
Reset value: 0000 0000b
Bit
Name
Description
7
SM0_1/FE_1 ^{Serial port 1 mode select}
6
SM1_1
SMOD0_1 (T3CON.6) = 0:
See Table 13-2. Serial Port 1 Mode Description for details.
SMOD0_1 (T3CON.6) = 1:
SM0_1/FE_1 bit is used as frame error (FE) status flag. It is cleared by
software.
0 = Frame error (FE) did not occur.
1 = Frame error (FE) occurred and detected.
5
SM2_1
Multiprocessor communication mode enable
The function of this bit is dependent on the serial port 1 mode.
Mode 0:
No effect.
Mode 1:
This bit checks valid stop bit.
0 = Reception is always valid no matter the logic level of stop bit.
1 = Reception is valid only when the received stop bit is logic 1 and
the received data matches “Given” or “Broadcast” address.
Mode 2 or 3:
For multiprocessor communication.
0 = Reception is always valid no matter the logic level of the 9^th bit.
1 = Reception is valid only when the received 9^th bit is logic 1 and
the received data matches “Given” or “Broadcast” address.
4
REN_1
Receiving enable
0 = Serial port 1 reception Disabled.
1 = Serial port 1 reception Enabled in Mode 1,2, or 3. In Mode 0, reception is
initiated by the condition REN_1 = 1 and RI_1 = 0.
3
TB8_1
9^th transmitted bit
This bit defines the state of the 9^th transmission bit in serial port 1 Mode 2 or 3.
It is not used in Mode 0 or 1.
2
RB8_1
9^th received bit
The bit identifies the logic level of the 9^th received bit in serial port 1 Mode 2 or
3. In Mode 1, RB8_1 is the logic level of the received stop bit. SM2_1 bit as
logic 1 has restriction for exception. RB8_1 is not used in Mode 0.
1
TI_1
Transmission interrupt flag
This flag is set by hardware when a data frame has been transmitted by the
serial port 1 after the 8^th bit in Mode 0 or the last data bit in other modes. When
the serial port 1 interrupt is enabled, setting this bit causes the CPU to execute
the serial port 1 interrupt service routine. This bit must be cleared manually via
software.
Jun 26, 2017
Page 121 of 267
Rev. 1.02