TSL2583FN Datasheet, PDF (12/33 Pages) List of Unclassifed Manufacturers – LIGHT-TO-DIGITAL CONVERTER

TSL2581, TSL2583
LIGHT-TO-DIGITAL CONVERTER
TAOS134A − JULY 2012
Control Register (00h)
The CONTROL register primarily used to power the TSL258x device up and down as shown in Table 4.
Table 4. Control Register
Bit : 7
6
5
4
3
2
1
0
Address
00h
FIELD
lid ^Reserved
ADC_INTR
ADC_VALID
a _Reserved
v ^ADC_EN
POWER
Reserved
ADRCe_sINvTR ADC_VALID
Reserved
ADC_EN POWER
Reset
00h
BIT
DESCRIPTION
7:6
Reserved. Write as 0.
5
ADC Interrupt. Read only. Indicates that the device is asserting an interrupt.
4
ADC Valid. Read only. Indicates that the ADC channel has completed an integration cycle.
3:2
Reserved. Write as 0.
1
ADC Enable. This field enables the two ADC channels to begin integration. Writing a 1 activates the ADC
channels, and writing a 0 disables the ADCs.
0
Power On. Writing a 1 powers on the device, and writing a 0 turns it off.
ill NOTE: ADC_EN and POWER must be asserted before the ADC changes will operate correctly. After POWER is asserted, a 2-ms delay is
required before asserting ADC_EN.
t _{NOTE: The TSL258x device registers should be configured before ADC_EN is asserted.}
G _{s Timing Register (01h)}
A ^t _{The TIMING register controls the internal integration time of the ADC channels in 2.7-ms increments. The}
s ^{n TIMING register defaults to 00h at power on.}
m ^{te Bit: 7}
a ^{n Address}
01h
o _FIELD
BIT
Technical ^{c ATIME}
7:0
Table 5. Timing Register
6
5
4
3
2
1
0
ATIME
Reset
00h
DESCRIPTION
Integration Cycles. Specifies the integration time in 2.7-ms intervals. Time is expressed as a 2’s
complement number. So, to quickly work out the correct value to write: (1) determine the number of
2.7-ms intervals required, and (2) then take the 2’s complement. For example, for a 1 × 2.7-ms interval,
0xFF should be written. For 2 × 2.7-ms intervals, 0xFE should be written. The maximum integration time
is 688.5 ms (00000001b).
Writing a 0x00 to this register is a special case and indicates manual timing mode. See CONTROL and
MANUAL INTEGRATION TIMER Registers for other device options related to manual integration.
INTEG_CYCLES
−
1
2
19
37
74
148
255
TIME
Manual integration
2.7 ms
5.4 ms
51.3 ms
99.9 ms
199.8 ms
399.6 ms
688.5 ms
00000000
11111111
11111110
11101101
11011011
10110110
01101100
00000001
VALUE
NOTE: The Send Byte protocol cannot be used when ATIME is greater than 127 (for example ATIME[7] = 1) since the upper bit is set aside for
write transactions in the COMMAND register.
The LUMENOLOGY r Company
r
Copyright E 2012, TAOS Inc.
r
www.taosinc.com
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