AT25F512B_12 Datasheet, PDF (12/34 Pages) List of Unclassifed Manufacturers – 512-Kbit 2.7V Minimum SPI Serial Falsh Memory

9.2 Write Disable
The Write Disable command is used to reset the Write Enable Latch (WEL) bit in the Status Reg-
ister to the logical “0” state. With the WEL bit reset, all Byte/Page Program, erase, Program OTP
Security Register, and Write Status Register commands will not be executed. Other conditions
can also cause the WEL bit to be reset; for more details, refer to the WEL bit section of the Sta-
tus Register description.
To issue the Write Disable command, the CS pin must first be asserted and the opcode of 04h
must be clocked into the device. No address bytes need to be clocked into the device, and any
data clocked in after the opcode will be ignored. When the CS pin is deasserted, the WEL bit in
the Status Register will be reset to a logical “0”. The complete opcode must be clocked into the
device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte
boundary (multiples of eight bits); otherwise, the device will abort the operation and the state of
the WEL bit will not change.
Figure 9-2. Write Disable
CS
SCK
SI
SO
01234567
OPCODE
00000100
MSB
HIGH-IMPEDANCE
9.3 Block Protection
The device can be software protected against erroneous or malicious program or erase opera-
tions by utilizing the Block Protection feature of the device. Block Protection can be enabled or
disabled by using the Write Status Register command to change the value of the Block Protec-
tion (BP0) bit in the Status Register. The following table outlines the two states of the BP0 bit
and the associated protection area.
Table 9-1. Memory Array Protection
Protection Level
BP0
None
0
Full Memory
1
Protected Memory Address
None
00000h - 00FFFFh
When the BP0 bit of the Status Register is in the logical “1” state, the entire memory array will be
protected against program or erase operations. Any attempts to send a Byte/Page Program
command, a Block Erase command, or a Chip Erase command will be ignored by the device.
As a safeguard against accidental or erroneous protecting or unprotecting of the memory array,
the BP0 bit itself can be locked from updates by using the WP pin and the BPL (Block Protection
Locked) bit of the Status Register (see “Protected States and the Write Protect Pin” on page 13
for more details).
12 AT25F512B
3689D–DFLASH–11/2012