AT25DQ161_13 Datasheet, PDF (12/65 Pages) List of Unclassifed Manufacturers – Minimum SPI Serial Flash Memory with Dual-I/O and Quad-I/O Support

7.3 Quad-Output Read Array
The Quad-Output Read Array command is similar to the Dual-Output Read Array command and can be used to
sequentially read a continuous stream of data from the device by simply providing the clock signal once the initial starting
address has been specified. Unlike the Dual-Output Read Array command, however, the Quad-Output Read Array
command allows four bits of data to be clocked out of the device on every clock cycle rather than two.
The Quad-Output Read Array command can be used at any clock frequency up to the maximum specified by f_RDQO. To
perform the Quad-Output Read Array operation, the CS pin must first be asserted and the opcode of 6Bh must be
clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the
starting address location of the first byte to read within the memory array. Following the three address bytes, a single
dummy byte must also be clocked into the device.
After the three address bytes and the dummy byte have been clocked in, additional clock cycles will result in data being
output on the I/O_3-0 pins. The data is always output with the MSB of a byte first, and the MSB is always output on the I/O₃
pin. During the first clock cycle, bit 7 of the first data byte will be output on the I/O₃ pin while bits 6, 5, and 4 of the same
data byte will be output on the I/O₂, I/O₁, and I/O₀ pins, respectively. During the next clock cycle, bits 3, 2, 1, and 0 of the
first data byte will be output on the I/O₃, I/O₂, I/O₁, and I/O₀ pins, respectively. The sequence continues with each byte of
data being output after every two clock cycles. When the last byte (1FFFFFh) of the memory array has been read, the
device will continue reading back at the beginning of the array (000000h). No delays will be incurred when wrapping
around from the end of the array to the beginning of the array.
Deasserting the CS pin will terminate the read operation and put the I/O_3-0 pins into a high-impedance state. The CS pin
can be deasserted at any time and does not require that a full byte of data be read.
Figure 7-5. Quad-Output Read Array
CS
SCK
I/O₀
(SI)
I/O₁
(SO)
I/O₂
(WP)
I/O₃
(HOLD)
0 1 2 3 4 5 6 7 8 9 10 11 12
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
Opcode
Address Bits A23-A0
Don't Care
Byte 1 Byte 2 Byte 3 Byte 4 Byte 5
Out Out Out Out Out
0 1 1 0 1 0 1 1AAAAAA
MSB
MSB
A A A X X X X X X X X D4 D0 D4 D0 D4 D0 D4 D0 D4 D0
MSB
High-impedance
D5 D1 D5 D1 D5 D1 D5 D1 D5 D1
High-impedance
D6 D2 D6 D2 D6 D2 D6 D2 D6 D2
High-impedance
D7 D3 D7 D3 D7 D3 D7 D3 D7 D3
MSB MSB MSB MSB MSB
AT25DQ161 [DATASHEET] 12
8671D–DFLASH–1/2013