ML7344C Datasheet, PDF (118/151 Pages) List of Unclassifed Manufacturers – Sub-GHz band short range wireless transceiver IC

FEDL7344C/E/J-04
ML7344C/E/J
(4) ACK transmission
ACK TX flow is as follows. During RX, ACK frame can be set in the TX FIFO.
START
RX FIFO trigger setting *1
[RXFIFO_THRH: B0 0x19]
[RXFIFO_THRL: B0 0x1A]
* In case of using interrupt,
FIFO-Full interrupt notification should be ON.
RX_ON issue*2 ^{*2 Please refer to RF state transition wait}
[RF_STATUS: B0 0x0B]
flow.
No
FIFO-Full interrupt?
INT[5] [INT_SOURCE_GRP1: B0 0x0D]
Yes
Read RX data *3
[RD_FIFO:B0 0x7F]
*3 read address field to
check length and
packet destination.
From RX flow
No
Self addressed?
Yes
Write TX data *4
[WR_TX_FIFO:B0 0x7C]
*4 ACK frame is set to TX FIFO.
No
RX completion (INT[8])? *5
*5 Please refer the following
[INT_SOURCE_GRP2: B0 0x0E(0)]
“NOTE”
Yes
CRC error (INT[9])?
Yes
[INT_SOURCE_GRP2] B0 0x0E(1)]
*6 Please refer to RF state
transition wait flow.
No
TX_ON issue *6
[RF_STATUS: B0 0x0B]
INT[8] and [9] clear
[INT_SOURCE_GRP2: B0 0x0E]
No
TX completion (INT[16])?
[INT_SOURCE_GRP3] B0 0x0F(0)]
Yes
Clear TX FIFO pointer
[STATE_CLR: B0 0x16(0)]
TRX_OFF issue
[RF_STATUS: B0 0x0B]
Read all RX data
[RD_FIFO:B0 0x7F]
Yes
Read RX data?
No
Clear RX FIFO pointer
[STATE_CLR: B0 0x16(1)]
END
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