IDT70V658S10DRG Datasheet, PDF (11/24 Pages) List of Unclassifed Manufacturers – HIGH-SPEED 3.3V 128/64/32K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM

IDT70V659/58/57S
High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range⁽⁵⁾
Symbol
Parameter
70V659/58/57S10 70V659/58/57S12 70V659/58/57S15
Com'l Only
Com'l
Com'l
& Ind
& Ind
Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC
Read Cycle Time
10
____
12
____
15
____
ns
tAA
Address Access Time
____
10
____
12
____
15
ns
tACE
Chip Enable Access Time⁽³⁾
____
10
____
12
____
15
ns
tABE
Byte Enable Access Time⁽³⁾
____
5
____
6
____
7
ns
tAOE
Output Enable Access Time
____
5
____
6
____
7
ns
tOH
Output Hold from Address Change
tLZ
Output Low-Z Time^(1,2)
tHZ
Output High-Z Time^(1,2)
tPU
Chip Enable to Power Up Time⁽²⁾
tPD
Chip Disable to Power Down Time⁽²⁾
tSOP
Semaphore Flag Update Pulse (OE or SEM)
3
____
3
____
3
____
ns
0
____
0
____
0
____
ns
0
4
0
6
0
8
ns
0
____
0
____
0
____
ns
____
10
____
10
____
15
ns
____
4
____
6
____
8
ns
tSAA
Semaphore Address Access Time
3
10
3
12
3
20
ns
4869 tbl 12
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage⁽⁵⁾
70V659/58/57S10 70V659/58/57S12 70V659/58/57S15
Com'l Only
Com'l
Com'l
& Ind
& Ind
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Unit
WRITE CYCLE
tWC
Write Cycle Time
tEW
Chip Enable to End-of-Write⁽³⁾
10
____
12
____
15
____
ns
8
____
10
____
12
____
ns
tAW
Address Valid to End-of-Write
tAS
Address Set-up Time⁽³⁾
8
____
10
____
12
____
ns
0
____
0
____
0
____
ns
tWP
Write Pulse Width
8
____
10
____
12
____
ns
tWR
Write Recovery Time
0
____
0
____
0
____
ns
tDW
Data Valid to End-of-Write
tDH
Data Hold Time⁽⁴⁾
tWZ
Write Enable to Output in High-Z^(1,2)
tOW
Output Active from End-of-Write^(1,2,4)
6
____
8
____
10
____
ns
0
____
0
____
0
____
ns
____
4
____
4
____
4
ns
0
____
0
____
0
____
ns
tSWRD
SEM Flag Write to Read Time
5
____
5
____
5
____
ns
tSPS
SEM Flag Contention Window
5
____
5
____
5
____
ns
NOTES:
4869 tbl 13
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranted by device characterization, but is not production tested.
3. To access RAM, CE= VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage
and temperature, the actual tDH will always be smaller than the actual tOW.
5. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 6 for details.
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