TRW-24G2 Datasheet, PDF (10/22 Pages) List of Unclassifed Manufacturers – Low Power High Performance 2.4 GHz GFSK Transceiver

the PTX goes directly to standby-I mode after
5.1.5 CRC
transmitting the packet and the PRX does not
transmit an ACK packet when it receives the
packet.
The CRC is the error detection mechanism in
the packet. The number of bytes in the CRC is
5.1.4 Payload
l _{The payload is the user defined content of the}
packet. It can be 0 to 32 bytes wide, and it is
ia ^{transmitted on-air as it is uploaded}
(unmodified) to the device.
nt ^{The TRW-24G2 provides two alternatives for}
handling payload lengths, static and dynamic
e _{payload length. The static payload length of}
each of six data pipes can be individually set.
id _{The default alternative is static payload length.}
f _{With static payload length all packets between}
n ^{n a transmitter and a receiver have the same}
length. Static payload length is set by the
o _io RX_PW_Px registers. The payload length on
t ^{the transmitter side is set by the number of}
C ^{bytes clocked into the TX_FIFO and must}
u equal the value in the RX_PW_Px register on
the receiver side. Each pipe has its own
G _ib ^{payload length.}
IN ^{r Dynamic Payload Length (DPL) is an}
t _{alternative to static payload length. DPL}
enables the transmitter to send packets with
H ^{is variable payload length to the receiver. This}
means for a system with different payload
lengths it is not necessary to scale the packet
S D _{length to the longest payload.}
N ^t _{With DPL feature the TRW-24G2 can decode}
E ^{o the payload length of the received packet}
automatically instead of using the RX_PW_Px
N ^{registers. The MCU can read the length of the}
received payload by using the command:
W_{R_RX_PL_WID.}
o _{In order to enable DPL the EN_DPL bit in the}
D FEATURE register must be set. In RX mode
set by the CRCO bit in the CONFIG register.
It may be either 1 or 2 bytes and is calculated
over the address, Packet Control Field, and
Payload.
The polynomial for 1 byte CRC is X⁸ + X² +
X + 1. Initial value is 0xFF.
The polynomial for 2 byte CRC is X¹⁶ + X¹² +
X⁵ + 1. Initial value is 0xFFFF.
No packet is accepted by receiver side if the
CRC fails.
5.2 Packet Handling
TRW-24G2 uses burst mode for payload
transmission and receive.
The transmitter fetches payload from TX FIFO,
automatically assembles it into packet and
transmits the packet in a very short burst
period with 1Mbps or 2Mbps air data rate.
After transmission, if the PTX packet has the
NO_ACK flag set, TRW-24G2 sets TX_DS
and gives an active low interrupt IRQ to MCU.
If the PTX is ACK packet, the PTX
needs receive ACK from the PRX and then
asserts the TX_DS IRQ.
The receiver automatically validates and
disassembles received packet, if there is a
valid packet within the new payload, it will
write the payload into RX FIFO, set RX_DR
and give an active low interrupt IRQ to MCU.
When auto acknowledge is enabled
(EN_AA=1), the PTX device will
automatically wait for acknowledge packet
after transmission, and re-transmit original
the DYNPD register has to be set. A PTX that
packet with the delay of ARD until an
transmits to a PRX with DPL enabled must
acknowledge packet is received or the number
have the DPL_P0 bit in DYNPD set.
of re-transmission exceeds a threshold ARC. If
the later one happens, TRW-24G2 will set
MAX_RT and give an active low interrupt
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