NT1080 Datasheet, PDF (10/22 Pages) List of Unclassifed Manufacturers – 8-bit Microcontroller

NT1080
After finishing 2nd byte data transmission, Start signal is needed before sending next 3rd byte data.
SCL signal will change to logic 0 when 3rd byte data transmission is done. SCL signal will be
released till 4^th output data is ready. The first host could send logic 1 on SCL and monitor SCL
changing to logic 1 to receive 1^st bit. Note that Master should send a logic 1, NACK signal, on the
9th clock signal of the 4th byte.
5.3 Continual-Read
This is a 4-byte data combination when Master continually reads Slave. Figure 5-3 shows that the
first byte as device address and write-status; the second byte as memory address; the third byte as
device address and read-status. From the fourth byte, Slave will keep output data with Master
keeping sending ACK and SCL clock signal. The memory address will be automatically increased.
SDA
SCL
Byte1 Device address Byte2 Memory address
Byte3 Device address
…...
Byte4 Data 1
Byte Data n
Figure 5-3 Continual-Read Mode
5.4 I²C Circuit
The pins of I²C are SDA and SCL with Open-Drain mode which requires pull-high resistor on the I²C
bus.
VDD
SDA
SCL
R_UP
R_UP
SDA
SCL
Host
SDA
SCL
Nu-Touch
SDA
SCL
Other Device
Figure 5-4 I²C Bus Connection
Oct 26, 2015
Page 10 of 22
Rev 1.0