ASC7511 Datasheet, PDF (10/19 Pages) List of Unclassifed Manufacturers – LOW- OLTAGE 2-WIRE DIGITAL TEMPERATURE SENSOR

aSC7511
any transitions on the SDA line can only occur when SCL is
low. The exceptions to this rule are when the master device
issues a start or stop condition. Note that the slave device
cannot issue a start or stop condition.
The aSC7511 supports packet error checking (PEC) per
the SMBus protocol. It will interpret the PEC byte when
provide and respond with a PEC byte when expected by
the master. The PEC byte is calculated using CRC-8 and
conforms to the frame check sequence with the polynomial:
C(x) = x⁸ + x² + x¹ + 1
Refer to SMBus specification 2.0 for more details.
SMBus Definitions
register’s content is automatically set to the value of the
first byte following the R/ W bit being set to 0.
After the aSC7511 sends an ACK in response to receiving
the address and R/ W bit, the master device must transmit
an appropriate 8-bit address pointer value as explained in
the Registers section of this data sheet. The aSC7511 will
send an ACK after receiving the new pointer data.
The register address pointer set operation is illustrated in
Figure 2. If the address pointer is not a valid address the
aSC7511 will internally terminate the operation. Also recall
that the address register retains the current address pointer
value between operations. Therefore, once a register is
being pointed to, subsequent read operations do not
require another Address Pointer set cycle.
The following are definitions for some general SMBus
terms:
Writing to Registers
Start Condition: This condition occurs when the SDA line
transitions from high to low while SCL is high. The master
device uses this condition to indicate that a data transfer is
about to begin.
Stop Condition: This condition occurs when the SDA line
transitions from low to high while SCL is high. The master
device uses this condition to signal the end of a data
transfer.
Acknowledge and Not Acknowledge: When data are
transferred to the slave device it sends an “acknowledge”
(ACK) after receiving each byte. The receiving device
sends an ACK by pulling SDA low for one clock. Following
the last byte, a master device sends a "not acknowledge"
(NACK) followed by a stop condition. A NACK is indicated
by forcing SDA high during the clock after the last byte.
Slave Address
Each slave device on the bus has a unique 7-bit SMBus
slave address. The aSC7511’s slave address is 4C hex.
Writing to and Reading from the aSC7511
All read and write operations must begin with a start
condition generated by the master device. After the start
condition, the master device must immediately send a
slave address (7-bits) followed by a R/ W bit. If the slave
address matches the address of the aSC7511, it sends an
ACK by pulling the SDA line low for one clock. Read or
write operations may contain one- or two-bytes. See
Figures 2 through 6 for timing diagrams for all aSC7511
operations.
Setting the Register Address Pointer
For all operations, the address pointer stored in the
address pointer register must be pointing to the register
address that is going to be written to or read from. This
All writes must start with a pointer set as described
previously, even if the pointer is already pointing to the
desired register. The sequence is described in Figure 3.
Immediately following the pointer set, the master must
begin transmitting the data to be written. After transmitting
each byte of data, the master must release the SDA line for
one clock to allow the aSC7511 to acknowledge receiving
the byte. The write operation should be terminated by a
stop condition from the master.
Reading from Registers
To read from a register other than the one currently being
pointed to by the address pointer register, a pointer set
sequence to the desired register must be done as
described previously. Immediately following the pointer
set, the master must perform a repeat start condition that
indicates to the aSC7511 that a read is about to occur. It is
important to note that if the repeat start condition does not
occur, the aSC7511 will assume that a write is taking place,
and the selected register will be overwritten by the
upcoming data on the data bus. The read sequence is
described in Figure 4. After the start condition, the master
must again send the device address and read/write bit.
This time the R/ W bit must be set to 1 to indicate a read.
The rest of the read cycle is the same as described in the
previous paragraph for reading from a preset pointer
location.
If the pointer is already pointing to the desired register, the
master can read from that register by setting the R/ W bit
(following the slave address) to a 1. After sending an ACK,
the aSC7511 will begin transmitting data during the
following clock cycle. After receiving the 8 data bits, the
master device should respond with a NACK followed by a
stop condition.
If the master is reset while the aSC7511 is in the process of
being read, the master should perform an SMBus reset.
This is done by holding the data or clock low for more than
© Andigilog, Inc. 2006
- 10 -
www.andigilog.com
August 2006 - 70A04010