ZVNL120GTA Datasheet, PDF (1/3 Pages) List of Unclassifed Manufacturers – SOT223 N-CHANNEL ENHANCEMENT MODE LOW THRESHOLD VERTICAL DMOS FET

SOT223 N-CHANNEL ENHANCEMENT MODE
LOW THRESHOLD VERTICAL DMOS FET
ISSUE 2 - JANUARY 1996 7
FEATURES
* V_DS - 200V
* R_DS(ON) - 10Ω
PARTMARKING DETAIL - ZVNL120
ZVNL120G
D
S
D
G
ABSOLUTE MAXIMUM RATINGS.
PARAMETER
SYMBOL
VALUE
UNIT
Drain-Source Voltage
V_DS
200
V
Continuous Drain Current at T_amb=25°C
I_D
320
mA
Pulsed Drain Current
I_DM
2
A
Gate-Source Voltage
V_GS
± 20
V
Power Dissipation at T_amb=25°C
P_tot
2
W
Operating and Storage Temperature Range T_j:T_stg
-55 to +150
°C
ELECTRICAL CHARACTERISTICS (at T_amb = 25°C unless otherwise stated).
PARAMETER
SYMBOL MIN. MAX. UNIT CONDITIONS.
Drain-Source Breakdown
Voltage
BV_DSS 200
V
I_D=1mA, V_GS=0V
Gate-Source Threshold Voltage V_GS(th) 0.5
Gate-Body Leakage
I_GSS
Zero Gate Voltage Drain
I_DSS
Current
1.5 V
I_D=1mA, V_DS= V_GS
100 nA V_GS=± 20V, V_DS=0V
10
µA V_DS=200V, V_GS=0V
100 µA V_DS=160V, V_GS=0V,
T=125°C(2)
On-State Drain Current(1)
I_D(on)
500
Static Drain-Source On-State R_DS(on)
10
Resistance (1)
10
Forward Transconductance(1)(2) g_fs
Input Capacitance (2)
C_iss
Common Source Output
Capacitance (2)
C_oss
200
85
20
mA V_DS=25V, V_GS=5V
Ω
V_GS=5V, I_D=250mA
Ω
V_GS=3V, I_D=125mA
mS V_DS=25V, I_D=250mA
pF
pF V_DS=25V, V_GS=0V, f=1MHz
Reverse Transfer Capacitance (2) C_rss
Turn-On Delay Time (2)(3)
t_d(on)
Rise Time (2)(3)
t_r
Turn-Off Delay Time (2)(3)
t_d(off)
Fall Time (2)(3)
t_f
7
pF
8
ns
8
ns
V_DD≈25V, I_D=250mA
20
ns
12
ns
(1) Measured under pulsed conditions. Width=300µs. Duty cycle ≤2% (2) Sample test.
(3) Switching times measured with 50Ω source impedance and <5ns rise time on a pulse generator
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