SPI-4 Datasheet, PDF (1/3 Pages) List of Unclassifed Manufacturers – Core w/ FIFOs V1.0 For Altera PLDs

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Product Brief
SPI-4 Phase 1
Core w/ FIFOs V1.0
For Altera PLDs
June 2001
Features
• OIF-compliant SPI-4 Phase 1
(compatible with AMCC FlexBUS-4)
with FIFOs
• ATM, Packet Over SONET (POS),
and Direct Data Mapping¹ modes
• Single- and multi-link operation,
scalable from 1 to 16 links.
• Programmable per-port bandwidth
allocation
• Programmable FIFO size with
programmable almost empty/almost
full thresholds.
• Programmable burst size
• Automatic link selection in the
Source block based on Source
FIFO threshold and flow control
information.
• 64-bit data bus width.
• Parity generation/checking over
data and control words
• Altera’s Atlantic Interface on user’s
side.
• Full synchronous design, exceeds:
Clk = 200 MHz
• Fully automatic test bench including
driver/monitor.
• Easy to use in Mux/Demux and
bridge functions
Standards Compliance
• OIF SPI-4 Phase 1
• AMCC FlexBUS-4
Benefits
• Faster FPGA and ASIC development for
improved time-to-market with FlexBUS-
4 functions
• Lower development cost through design
reuse
• Available source code licensing for easy
design integration and migration to gate
arrays or ASICs
• Ample design flexibility using control
signals and generics/parameters
• Verified functionality and standards
compliance
Description
The Optical Interworking Forum’s (OIF) SPI-
4 Phase 1 interface allows the
interconnection of Physical Layer devices to
Link Layer devices in 10Gb/s ATM, POS,
and Ethernet applications. Modelware’s
SPI-4 Phase 1 core performs the interface
functions on both sides of the interface as
shown in Figure 1and Figure 2.
PHY
Layer
Processor
PluriBus
Interface
Spi4
Tx
FIFO(s)
Spi4Tx
Spi4Rx
Rx
FIFO(s)
Line Tx
Data
SPI-4
I/F
Line Rx
Data
Link
Layer
Control
Status
Figure 1: SPI-4 Phase 1 PHY Layer Application
1 _{Direct Data Mapping is a raw data mode}
supported in AMCC’s Ganges device.