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SGP08G72D1BD2SA-BBRT Datasheet, PDF (1/17 Pages) List of Unclassifed Manufacturers – 8 GB DDR3 – registered ULP DIMM | |||
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preliminary Data Sheet
Rev.0.9 15.01.2014
8 GB DDR3 â registered ULP DIMM
240 Pin registered ULP DIMM
SGP08G72D1BD2SA-xxRT
8 GB in FBGA Technology
RoHS compliant
Options:
ï§ Data Rate / Latency
DDR3 1066 MT/s CL7
DDR3 1333 MT/s CL9
Marking
-BB
-CC
ï§ Module Density
8 GB with 18 dies and 2 ranks
ï§ Standard Grade
ï§ W-Grade
(TA) 0°C to 70°C
(TC) 0°C to 85°C
(TA) -40°C to 85°C
(TC) -40°C to 95°C *)
*) The refresh rate has to be doubled when 85°C<TC<95°C
Environmental Requirements:
ï§ Operating temperature (ambient)
Standard Grade
0°C to 70°C
W-Grade
-40°C to 85°C
ï§ Operating Humidity
10% to 90% relative humidity, non condensing
ï§ Operating Pressure
105 to 69 kPa (up to 10000 ft.)
ï§ Storage Temperature
-55°C to 100°C
ï§ Storage Humidity
5% to 95% relative humidity, non condensing
ï§ Storage Pressure
1682 PSI (up to 5000 ft.) at 50°C
Features:
ï§ 240-pin 72-bit DDR3 registered Dual-In-Line Double Data
Rate synchronous DRAM module for server applications
ï§ Module organization: dual rank 1G x 72
ï§ VDD = 1.5V ±0.075V, VDDQ 1.5V ±0.075V
ï§ 1.5V I/O ( SSTL_15 compatible)
ï§ Ultra Low Profile (ULP)
ï§ PCB connector with chamfer
ï§ JEDEC compatible DDR3 PLL/Register component with
parity bit support for address and control bus
ï§ Supports ECC error detection and correction
ï§ On-board I2C temperature sensor with integrated serial
presence-detect (SPD) EEPROM
ï§ Gold-contact pads
ï§ This module is fully pin and functional compatible to the
JEDEC PC3-10600 spec. and JEDEC- Standard MO-269.
(see www.jedec.org)
ï§ The pcb and all components are manufactured according
to the RoHS compliance specification [EU Directive
2002/95/EC Restriction of Hazardous Substances (RoHS)]
ï§ DDR3 - SDRAM component Samsung K4B4G0846D,
die Rev. D
ï§ 512Mx8 DDR3 SDRAM in PG-TFBGA-78 package
ï§ Programmable CAS Latency, CAS Write Latency, Additive
Latency, Burst Length and Burst Type.
ï§ On-Die-Termination (ODT) and Dynamic ODT for improved
signal integrity.
ï§ Refresh. Self Refresh and Power Down Modes.
ï§ ZQ Calibration for output driver and ODT.
ï§ System Level Timing Calibration Support via Write Leveling
and Multi Purpose Register (MPR) Read Pattern.
Figure: mechanical dimensions1
R 0.70mm
2.20mm
R 0.75mm
R 0.70mm
54.67mm
133.35mm
Swissbit AG
Industriestrasse 4
CH â 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
1the reference according MO269
www.swissbit.com
eMail: info@swissbit.com
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