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SEU02G64B3BH2MT-25R Datasheet, PDF (1/14 Pages) List of Unclassifed Manufacturers – 2GB DDR2 – SDRAM DIMM | |||
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Data Sheet
Rev.1.2 02.12.2010
2GB DDR2 â SDRAM DIMM
240 Pin UDIMM
SEU02G64B3BH2MT-25R
2GB PC2-6400 in FBGA Technology
RoHS compliant
Options:
ï§ Data Rate / Latency
DDR2 800 MT/s CL6
DDR2 667 MT/s CL5
Marking
-25
-30
ï§ Module Density
2048MB with 16 dies and 2 ranks
ï§ Standard Grade (Tc)
(TA)
0°C to 85°C
0°C to 70°C
Environmental Requirements:
ï§ Operating temperature (ambient)
Standard Grade
0°C to 70°C
ï§ Operating Humidity
10% to 90% relative humidity, noncondensing
ï§ Operating Pressure
105 to 69 kPa (up to 10000 ft.)
ï§ Storage Temperature
-55°C to 100°C
ï§ Storage Humidity
5% to 95% relative humidity, noncondensing
ï§ Storage Pressure
1682 PSI (up to 5000 ft.) at 50°C
Features:
ï§ 240-pin 64-bit DDR2 Dual-In-Line Double Data Rate
Synchronous DRAM Module
ï§ Module organization: dual rank 256M x 64
ï§ VDD = 1.8V ±0.1V, VDDQ 1.8V ±0.1V
ï§ 1.8V I/O ( SSTL_18 compatible)
ï§ Serial Presence Detect (SPD) EEPROM
ï§ Gold-contact pad
ï§ This module is fully pin and functional compatible to the
JEDEC PC2-6400 spec. and JEDEC- Standard MO-237.
(see www.jedec.org)
ï§ The pcb and all components are manufactured according
to the RoHS compliance specification
[EU Directive 2002/95/EC Restriction of Hazardous
Substances (RoHS)]
ï§ DDR2 - SDRAM component Micron
MT47H128M8CF-25 DIE-Rev.H
ï§ 128Mx8 DDR2 SDRAM in FBGA-60 package
ï§ Four bit prefetch architecture
ï§ DLL to align DQ and DQS transitions with CK
ï§ Eight internal device banks for concurrent operation
ï§ Programmable CAS latency (CL)
ï§ Posted CAS additive latency (AL)
ï§ WRITE latency = READ latency â 1 tCK
ï§ Programmable burst length: 4 or 8
ï§ Adjustable data-output drive strength
ï§ On-die termination (ODT)
Figure: mechanical dimensions1
1if no tolerances specified ± 0.15mm
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Fon: +41 (0) 71 913 0303
Fax: +41 (0) 71 913 0315
www.swissbit.com
eMail: info@swissbit.com
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