SEU02G64B3BF2SA-25R Datasheet, PDF (1/14 Pages) List of Unclassifed Manufacturers – 2GB DDR2 – SDRAM DIMM

Data Sheet
Rev.1.1 18.11.2010
2GB DDR2 – SDRAM DIMM
240 Pin DIMM
SEU02G64B3BF2SA-25R
2GB PC2-6400 in FBGA Technology
RoHS compliant
Options:
 Data Rate / Latency
DDR2 800 MT/s CL6
DDR2 667 MT/s CL5
Marking
-25
-30
 Module density
2048MB with 16 dies and 2 ranks
 Standard Grade (T_A)
(T_C)
0°C to 70°C
0°C to 85°C
Environmental Requirements:
 Operating temperature (ambient)
Standard Grade
0°C to 70°C
 Operating Humidity
10% to 90% relative humidity, noncondensing
 Operating Pressure
105 to 69 kPa (up to 10000 ft.)
 Storage Temperature
-55°C to 100°C
 Storage Humidity
5% to 95% relative humidity, noncondensing
 Storage Pressure
1682 PSI (up to 5000 ft.) at 50°C
Features:
 240-pin 64-bit Dual-In-Line Double Data Rate
synchronous DRAM Module
 Module organization: dual rank 256M x 64
 V_DD = 1.8V ±0.1V, V_DDQ 1.8V ±0.1V
 1.8V I/O ( SSTL_18 compatible)
 Auto Refresh (CBR) and Self Refresh 8k Refresh
every 64ms
 Serial Presence Detect with EEPROM
 Gold-contact pad
 This module is fully pin and functional compatible to
the JEDEC PC2-6400 spec. and JEDEC- Standard
MO-237. (see www.jedec.org)
 The pcb and all components are manufactured
according to the RoHS compliance specification
[EU Directive 2002/95/EC Restriction of Hazardous
Substances (RoHS)]
 DDR2 - SDRAM component SAMSUNG
K4T1G084QF DIE Rev. F
 128Mx8 DDR2 SDRAM in FBGA-60 package
 4-bit prefetch architecture
 DLL to align DQ and DQS transitions with CK
 Multiple internal device banks for concurrent operation
 Programmable CAS latency (CL)
 Posted CAS additive latency (AL)
 WRITE latency = READ latency – 1 t_CK
 Programmable burst length: 4 or 8
 Adjustable data-output drive strength
 On-die termination (ODT)
Figure: mechanical dimensions¹
Swissbit AG
Industiestrasse 4
CH-9552 Bronschhofen
Fon: [phone]
Fax: [phone]
1_{if no tolerances specified ± 0.15mm}
www.swissbit.com
eMail: [e-mail]
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