SDN12864L1B62MT-50 Datasheet, PDF (1/14 Pages) List of Unclassifed Manufacturers – 1024MB DDR SDRAM SO-DIMM

Data Sheet
Rev.1.1 04.02.2014
1024MB DDR SDRAM SO-DIMM
200Pin SO-DIMM
SDN12864L1B62MT-XXR
1024MB DDR PC-3200 in FBGA Technology
RoHS compliant
 Date Rate / Latency
 DDR 400 MHz CL3
 DDR 333 MHz CL2.5
Marking
-50
-60
 Module densitiy
1GB with 16 dies and 2 rank
 Standard Grade (T_A)
(T_C)
 E-Grade
(T_A)
(T_C)
 W-Grade
(T_A)
(T_C)
0°C to 70°C
0°C to 85°C
0°C to 70°C
0°C to 85°C
0°C to 70°C
0°C to 85°C
*) The refresh rate has to be doubled when 85°C<TC<95°C
Environmental Requirements:
 Operating temperature (TA)
Standatd Grade
0°C to 70°C
Grade E
0°C to 85°C
Grade W
-40°C to 85°C
Operating Humidity
10% to 90% relative humidity, noncondensing
 Operating Pressure
105 to 69 kPa (up to 10000 ft.)
 Storage Temperature
-55°C to 100°C
 Storage Humidity
5% to 95% relative humidity, noncondensing
 Storage Pressure
1682 PSI (up to 5000 ft.) at 50°C
Features:
 200-pin 64-bit DDR1 Small Outline Dual-In-Line Double
Data Rate Synchronous DRAM module
 Module organization: dual rank128M x 64
 VDD = 2.5V ±0.2V, VDDQ 2.5V ±0.2V
 VDD = 2.6V ±0.1V, VDDQ 2.6V ±0.1V (DDR400)
 2.5V I/O ( SSTL_2 compatible)
 Serial Presence Detect with EEPROM
 Gold-contact pads
 This module is fully pin and functional compatible to the
JEDEC PC-3200 spec. and JEDEC- Standard MO-224.
(see www.jedec.org)
 The pcb and all components are manufactured according
to the RoHS compliance specification [EU Directive
2002/95/EC Restriction of Hazardous Substances (RoHS)]
 DDR1 - SDRAM component Micron MT46V64M8BN-X:F
 64Mx8 DDR1 SDRAM in 60-ball FBGA package
 Internal, pipelined double-data-rate (DDR)
 2n pre-fetch architecture
 DLL to align DQ and DQS transitions with CK
 Bidirectional data strobe (DQS) transmitted/received with
data, source-synchronous data capture
 Differential clock inputs (CK and CK#)
 Commands entered on each positive CK edge
 Four internal banks for concurrent operation
 Data mask (DM) for masking write data
 Programmable burst length: 2,4 or 8
 Adjustable data-output drive strength
 ^FAⁱu^gto^urR^ee^:fr^Mes^eh^ch(C^aBⁿR^ic)^aa^l n^Dd^imSe^elⁿf ^sRⁱe^ofⁿre^ssh, 8k Refresh every
64ms
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Fon: [phone]
Fax: [phone]
1_{if no tolerances specified ± 0.15mm}
www.swissbit.com
email: [e-mail]
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