R8051XC Datasheet, PDF (1/8 Pages) List of Unclassifed Manufacturers – Configurable Microcontroller

Data Sheet
Electronic Design Department
Poland, 44-100 Gliwice, Dubois 16
Phone/Fax: [phone]
[e-mail]
www.evatronix.pl
January 8, 2008
R8051XC
Configurable Microcontroller
Overview
Optional Features and Peripherals
The R8051XC is a fast, configurable, single-chip 8-bit ♦
microcontroller core that can implement a variety of fast
processor variations executing the MCS® 51 instruction set.
The efficient core design runs an average of 8.1 times faster than
the 80C51. A rich set of optional features and peripherals enable
designers to closely match the core with their specific application
and hardware requirements (FPGA, ASIC, or structured ASIC).
These options include memory pointers, interrupts, interfaces for
serial communication, I2C and SPI interfaces, a timer system, I/O
ports, power management unit, multiplication-division unit,
watchdog timer, DMA controller and real-time clock. Integrated
on-chip debugging using either the native OCDS or FS2’s OCI is
also available.
♦
The R8051XC is an extension of our proven 8051 family of
processor cores, which have been successfully implemented in a
hundred different customer products. Designers can purchase
a custom configuration by selecting a set of options that best
♦
meets their needs, or choose from these three prepackaged
versions of the core:
♦
R8051XC-F is the fully-configurable version of the core,
with all options included.
♦
R8051XC-A matches our earlier R8051, with a set of
peripherals making it compatible with the Intel 80C31 (see ♦
details in the Configurations section).
R8051XC-B matches our earlier R80515 core, with a set of ^♦
peripherals making it compatible with the Siemens 80C515
and 80C517.
Representative ASIC implementation results for the different
configurations range from under 9,000 gates for the R8051XC-A
to under 55,000 for all available options (except debug). Speed
ranges from 250 to 350 MHz and above, depending on the
technology.
♦
Developed for easy reuse in ASIC and FPGA implementations, the
core is strictly synchronous, with positive-edge clocking, no
internal tri-states, and a synchronous reset.
Features
♦
♦ Eight-bit instruction decoder for MCS® 51 instruction set
♦ Executes instructions with one clock per cycle (versus twelve
for standard 80C51) for an average 8.1 times speed increase
♦ ALU performs 8-bit arithmetic and logical operations and
Boolean manipulations; 8-bit multiplication and division can be ♦
optionally removed to save silicon
♦ Flexible external memory interface can address up to 8MB of ♦
Program Memory and 8MB of Data Memory Space (when the ♦
extended memory option is included)
♦
♦ Can address up to 256 B of Internal Data Memory
♦
♦ SFR interface services 40 to 118 external Special Function
Registers (depending on configuration)
♦ Extensive core configurability: choose options as needed, or
get fully-configurable version
External Memory Interface
Addresses up to 8 MB of Program Memory (when using
memory banking)
Addresses up to 8 MB of Data Memory (when using
memory banking)
One, two, or eight Data Pointers for fast data block
transfer
Additional Arithmetic Unit supporting Data Pointers
auto-increment/-decrement and auto-switch
Supports external DMA controller through HOLD
interface
Program memory write mode
Multiplication-Division Unit
16 x 16-bit multiplication
32/16- and 16/16-bit division
32-bit normalization and L/R shifting
Special Function Registers interface
Services from 40 to 118 External Special Function
Registers (depending on peripheral configuration)
Interrupt Controller: four priority levels with eighteen interrupt
sources, or two priority levels with six sources
Power Management Unit with power-down modes (IDLE and
STOP)
Interface for on-chip debug: native On-Chip Debug Support
(OCDS
Direct Memory Access (DMA) Controller
Up to eight independent channels
Read/Write Access to all memory spaces (incl. SFR)
Linear addressing (up to 8MB)
Address auto-increment/decrement
Synchronous/asynchronous Mode
Software Trigger/Hardware Trigger
16-bit Timers/Counters:
80C51-like Timers 0 and 1
80C515-like Timer 2; it includes a Compare/Capture Unit
with four 16-bit Compare registers for Pulse Width
Modulation; four external Capture inputs for Pulse Width
Measuring; and a 16-bit Reload register for Pulse
Generation
Input/Output ports
Up to four 8-bit I/O ports; alternate port functions, such
as external interrupts and the serial interface are
separated, providing extra port pins when compared
with the standard 8051
Serial 0: a full-duplex serial interface (80C51-like), equipped
with additional baud rate generator
Serial 1: an asynchronous-only version of Serial 0
15-bit programmable Watchdog timer
SPI Master/Slave interface
One or two I2C™ Master/Slave interfaces
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R8051XC-DSN-1HV28F26S00-200
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