PSB-64 Datasheet, PDF (1/2 Pages) List of Unclassifed Manufacturers – PCI-SCI Bridge Chips for System Area Networks

PSB-64
PCI-SCI Bridge Chips
for System Area Networks
Features and Benefits
• PCI 2.1 compliant, 64 bits, 33 MHz PCI bus
• ANSI/IEEE 1596-1992 Scalable Coherent
Interface (SCI) standard compliant
• ANSI/IEEE 1159.1 (JTAG) support
• Compatible with Dolphin Link Controllers
• Chaining (Read/Write) DMA Engine
• Up to 4096 map entries in offchip SRAM
• 4 - 512 KBytes page size
• Hostbridge capability (PCI arbiter, Event
reporter)
• Read prefetching/write gathering
• B-Link™ Compliant
Dolphin´s PCI-SCI Bridge (PSB) Chip provides a
reliable, very high bandwidth and low-latency
connection between PCI buses, making it ideally
suited for server clustering and high performance
system area network applications.
The PSB-64 chip is designed to meet the requirements
for high availability clustering and remote I/O
applications. In a unique architecture combining both
direct memory access (DMA) and remote memory
access (RMA), high performance message passing
protocols and transparent bus bridging operations are
supported. The PSB chip is based on the ANSI/IEEE
Scalable Coherent Interface (SCI) standard.
By use of the DMA controller chunks of memory can
be copied directly between PCI buses in a single copy
operation with no need for intermediate buffering in
adapter cards or buffer memories. This feature greatly
reduces latency and lowers overhead of data
transfers. The DMA controller supports both read and
write operations.
The remote memory access (RMA) feature of the PSB
enables ultra-low latency messaging and low
overhead and transparent I/O transfers. In RMA
mode, PCI bus memory transactions are converted
into corresponding SCI bus memory transactions
allowing two physically separate PCI buses to appear
as one. This feature allows applications to send data
between system memories without the use of
operating system services, thus greatly reducing
latency and overhead.
The PSB has built-in address translation, error
detection and protection mechanisms to support
highly reliable connections.