PCIE-7350 Datasheet, PDF (1/2 Pages) List of Unclassifed Manufacturers – 50 MHz 32-CH High-Speed Digital I/O Card

PCIe-7350
50 MHz 32-CH High-Speed Digital I/O Card
Features
■ x1 lane PCI Express® Interface
■ Maximum 50 MHz clock rate from internal timer or
100 MHz from external clock
■ 200 MB/s maximum throughput
■ Software selectable voltage level of 1.8 V, 2.5 V, and 3.3 V
■ 16-step phase shift in external clock mode
■ Per group (8-bit) input/output direction selectable
■ Supports I²C and SPI programmable serial interfaces for
external device communication
■ Scatter-gather DMA support
■ Flexible handshaking and external digital trigger modes
■ 8-channel auxiliary programmable I/O
■ Operating Systems
• Windows 7/Vista/XP/2000/2003 Server
■ Recommended Software
• VB.NET/VC.NET/VB/VC++/BCB/Delphi
• DAQBench
■ Driver Support
• PCIS-DASK for Windows
Introduction
ADLINK’s PCIe-7350 is a high-speed digital I/O board with 32-channel bi-direction parallel I/O lines. The data rate can
achieve up to 200 MB/s through the x1 PCI Express® interface. The clock rate can support up to 50 MHz internal clock
or 100 MHz external clock, which is ideal for the applications of high-speed and large-scale digital data acquisition or
exchange, such as digital image capture, video playback and IC testing.
■ I/O Port Configuration & Level Shifting
The PCIe-7350’s initial status (power-up status) of the on-board 32-channel I/O lines is preset as input lines. The 32-channel
I/O lines are bi-direction and can be divided into four groups. Each group contains 8 channels and can be individually
configured as an input or output port. The PCIe-7350 also supports software selectable logic level of 1.8 V, 2.5 V, and 3.3 V.
When you select one of the logic levels, all the four groups will be at the same logic level you choose. In digital output
mode, the outputs are tri-stated when the digital output lines are disabled. The programmable I/O direction and logic
levels provide a flexible interface to the device under test (DUT).
■ Maximum Data Transfer Rate
The PCIe-7350 can support a maximum of 200 MB/s throughput along with a 32-bit data width at a maximum 50 MHz
internal clock rate or 8/16-bit data width at a maximum 100 MHz external clock rate. The combination scatter-gather
bus-mastering DMA, deep on-board 8 k-sample FIFO size, and x1 PCI Express^® interface guarantee no data loss during
sustained high-speed data processing.
■ Phase Delay
The PCIe-7350 features phase shifting of external sample clock or
internal sample clock exporting, which allow you to optimize the
acquisition/generation timing in high-speed data transfer applications.
The phase shifting of sample clock is capable of up to 16-steps
adjustment– that is, the phase shifting can be adjusted from 22.5
degrees to 337.5 degrees. This feature thus prevents sampling at the
transition state of the acquired data to ensure sample timing is valid
and in stable condition. The left timing diagram is the examples of
180-degree phase shift for digital data acquisition and generation.
■ I²C & SPI Serial Interfaces
PCIe-7350’s application function I/O (AFI) can be configured as a I²C or SPI master node. The I²C interface supports fast mode
and uses two bi-direction lines called SCL (serial clock) and SDA (serial data). The SPI interface uses three-wire signaling called
SCK (serial clock), SI (serial data input), and SO (serial data output). Communication with peripheral devices can be directly
performed through the PCIe-7350’s built-in I²C or SPI protocols along with provided APIs.
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PCIe-7350 Block Diagram