ML67Q4060 Datasheet, PDF (1/37 Pages) List of Unclassifed Manufacturers – 32-bit General-Purpose ARM-Based Microcontroller

ML67Q4060/61/50/51
32-bit General-Purpose ARM-Based Microcontroller
FEDL67Q4060-01
Issue Date: Jan. 21, 2008
OVERVIEW
This LSI is a general-purpose microcontroller that integrates peripheral functions such as I2C, I2S, and various
serial interfaces. It uses the ARM7TDMITM 32-bit RISC CPU developed by ARM Limited as its core.
The following describes the features of the ML67Q4050/ML67Q4060 Series.
FEATURES
 CPU
ATM7TDMI up to 33.33MHz
 Internal memory
16KB RAM processor bus connection
Built-in Flash ROM processor bus connection of the 128KB(ML67Q4051
and ML67Q4061) or 64KB (ML67Q4050 and ML67Q4060)
 External memory controller (Function for the ML67Q4050 series only)
Setting of programmable access timing for each space
ROM (FLASH) access function
SRAM access function
External I/O access function
 Interrupt controller/extended interrupt controller
FIQ: 1 source (NMI pin)
IRQ: 31 sources (40 sources for the ML67Q4050 Series)
Seven levels of interrupt priorities can be set for each interrupt source.
 System timer
16-bit auto-reload timer:  1ch
 SIO (UART)
Full-duplex start-stop synchronization method
 DMA controller
2ch
 Watchdog timer
16-bit timer
 A/D converter
10-bit sequential comparison type  4ch
 I2C bus controller
Philips I2C bus specification Ver 2.1 conformed controller
 Flexible timer
16-bit timer  6ch
Operable in each of the modes, Auto Reload Timer (ART)/Compare Out
(CMO)/Pulse Width Modulation (PWM)/Capture (CAP)
 RTC
Generates 1 second from 32.768 kHz
 I2S transmit/receive
Connection interface for general-purpose DACs/ADCs. Conforms to
Philips I2S (the Inter-IC Sound) specification
 GPIO
Built-in GPIO of 8 bits  1ch, 7 bits  2ch, and 6 bits  3ch
 UART
2 channels of serial communication function with FIFO
 SPI
2 channel of full duplex serial peripheral interface
 Clock
Main clock oscillator (16 to 33.333MHz)
RTC clock oscillator (32.768kHz clock)
 Power management
Power saving mode
CPU halt mode: Stops only the CPU clock.
STOP mode: Stops all the clocks of the chip except RTC
 Package
64pin TQFP(TQFP64-P-1010-0.50-K)
84pin LFBGA(P-LFBGA84-0909-0.80)
64pin WCSP(P-VFBGA64-5.09  4.84-0.50-W, P-VFLGA64-5.09 
4.84-0.50-W)
144pin LQFP(LQFP144-P-2020-0.50-ZK)
144-pin LFBGA (P-LFBGA144-1111-0.80)
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