ML620Q536 Datasheet, PDF (1/9 Pages) List of Unclassifed Manufacturers – Ultra Low Power 16-bit Microcontroller

ML620Q53x/54x/Q55x (x:6,8)
Ultra Low Power 16-bit Microcontroller
PEDL620Q53x_54x_55x-06
Issue Date：July 30,2015
Preliminary
GENERAL DESCRIPTION
This LSI family is a high-performance 16-bit CMOS microcontroller into which rich peripheral circuits, such as synchronous
serial port, UART, I2C bus interface (master), supply voltage level detect circuit, RC oscillation type A/D converter, and
successive approximation type A/D converter are incorporated around 16-bit CPU nX-U16/100.
The CPU nX-U16/100 is capable of efficient instruction execution in 1-instruction 1-clock mode by 3-stage pipe line
architecture parallel processing. The rich peripheral circuits such as I/O port, Serial interface and Timers are installed. So this
LSI family is most suitable for consumer and industry devices that are required for multi-actuation system. And, this LSI has a
data flash-memory fill area by software which can be written in.
The on-chip debug function that is installed enables program debugging and programming.
FEATURES
• CPU
− 16-bit RISC CPU (CPU name: nX-U16/100)
− Instruction system: 16-bit instructions
− Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit operation, bit
logic operations, jump, conditional jump, call return stack operation, arithmetic shift, and so on.
− On-Chip debugs function
− Minimum instruction execution time
30.5 µs (@ 32.768 kHz system clock)
62.5 ns (@16 MHz system clock)
• Built-in coprocessor for multiplication, division, and multiply-accumulate operations
− Signed or unsigned operation setting
− Multiplication: 16 bit x 16 bit (operation time 4 cycles)
− Division: 32 bit / 16 bit (operation time 8 cycles)
− Division: 32 bit / 32 bit (operation time 16 cycles)
− Multiply-accumulate (non-saturating): 16 bit x 16 bit + 32bit (operation time 4 cycles)
− Multiply-accumulate (saturating): 16 bit x 16 bit + 32 bit (operation time 4 cycles)
• Internal memory
− Supports ISP function (re-writing the program memory area by software)
− Number of segments
Product name
Flash memory
Program area^*
Data area
ML620Q558
256KB (128K × 16bit)
2KB (1K × 16bit)
ML620Q556
128KB (64K × 16bit)
2KB (1K × 16bit)
ML620Q548
256KB (128K × 16bit)
2KB (1K × 16bit)
ML620Q546
128KB (64K × 16bit)
2KB (1K × 16bit)
ML620Q538
256KB (128K × 16bit)
2KB (1K × 16bit)
ML620Q536
128KB (64K × 16bit)
2KB (1K × 16bit)
*: including 1KB of unusable test area
SRAM
20KB (10K × 16bit)
10KB (5K × 16bit)
20KB (10K × 16bit)
10KB (5K × 16bit)
20KB (10K × 16bit)
10KB (5K × 16bit)
STATUS
Under developing
Under planning
Under planning
Under developing
Under planning
Under planning
• Interrupt controller (INTC)
− 1 non-makeable interrupt sources (Internal source: WDT)
− 52 makeable interrupt sources (Internal sources: 44, External sources: 8)
− External interrupts and comparator allow edge selection and sampling selection
− Priority level (4-level) can be set for each interrupt
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