KVR16LN11K2-8 Datasheet, PDF (1/2 Pages) List of Unclassifed Manufacturers – 8GB (4GB 1Rx8 512M x 64-Bit x 2 pcs.)

Memory Module Specifications
KVR16LN11K2/8
8GB (4GB 1Rx8 512M x 64-Bit x 2 pcs.)
PC3L-12800 CL11 240-Pin DIMM Kit
DESCRIPTION
SPECIFICATIONS
ValueRAM's KVR16LN11K2/8 is a kit of two 512M x 64-bit
(4GB) DDR3L-1600 CL11 SDRAM (Synchronous DRAM), 1Rx8,
low voltage, memory modules, based on eight 512M x 8-bit
FBGA components per module. Total kit capacity is 8GB. The
SPDs are programmed to JEDEC standard latency DDR3-1600
timing of 11-11-11 at 1.35V or 1.5V. Each 240-pin DIMM uses
gold contact fingers. The electrical and mechanical specifica-
tions are as follows:
FEATURES
• JEDEC standard 1.35V (1.28V ~ 1.45V) and 1.5V (1.425V ~
1.575V) Power Supply
CL(IDD)
11 cycles
Row Cycle Time (tRCmin)
48.125ns (min.)
Refresh to Active/Refresh
Command Time (tRFCmin)
260ns (min.)
Row Active Time (tRASmin)
35ns (min.)
Maximum Operating Power @1.35V TBD W* (per module)
UL Rating
Operating Temperature
94 V - 0
0^o C to 85^o C
Storage Temperature
-55^o C to +100^o C
*Power will vary depending on the SDRAM.
• VDDQ = 1.35V (1.28V ~ 1.45V) and 1.5V (1.425V ~ 1.575V)
• 800MHz fCK for 1600Mb/sec/pin
• 8 independent internal bank
• Programmable CAS Latency: 11, 10, 9, 8, 7, 6
• Programmable Additive Latency: 0, CL - 2, or CL - 1 clock
• 8-bit pre-fetch
• Burst Length: 8 (Interleave without any limit, sequential with
starting address “000” only), 4 with tCCD = 4 which does not
allow seamless read or write [either on the fly using A12 or
MRS]
• Bi-directional Differential Data Strobe
• Internal(self) calibration : Internal self calibration through ZQ
pin (RZQ : 240 ohm ± 1%)
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower than TCASE 85°C,
3.9us at 85°C < TCASE < 95°C
• Asynchronous Reset
• _{PCB Height: 0.740” (18.75mm) or 1.180” (30.00mm)}
Important Information: The module defined in this data sheet is one of several configurations available under
this part number. While all configurations are compatible, the DRAM combination and/or the module height
may vary from what is described here.
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Document No. VALUERAM1443-001.B00 03/26/15 Page 1