KVR13R9S4L-8 Datasheet, PDF (1/2 Pages) List of Unclassifed Manufacturers – 8GB 1Rx4 1G x 72-Bit PC3-10600

Memory Module Specifications
KVR13R9S4L/8
8GB 1Rx4 1G x 72-Bit PC3-10600
CL9 Registered w/Parity 240-Pin DIMM
DESCRIPTION
This document describes ValueRAM's 1G x 72-bit (8GB)
DDR3L-1333 CL9 SDRAM (Synchronous DRAM), registered w/
parity, 1Rx4 ECC VLP memory module, based on eighteen 1G
x 4-bit FBGA components. The SPD is programmed to JEDEC
standard latency DDR3-1333 timing of 9-9-9 at 1.5V. This 240-
pin DIMM uses gold contact fingers. The electrical and me-
chanical specifications are as follows:
FEATURES
• JEDEC standard 1.5V (1.425V ~1.575V) Power Supply
• VDDQ = 1.5V (1.425V ~ 1.575V)
• 667MHz fCK for 1333Mb/sec/pin
• 8 independent internal bank
• Programmable CAS Latency: 9, 8, 7, 6
• Programmable Additive Latency: 0, CL - 2, or CL - 1 clock
• Programmable CAS Write Latency(CWL) = 7 (DDR3-1333)
• 8-bit pre-fetch
• Burst Length: 8 (Interleave without any limit, sequential with
starting address “000” only), 4 with tCCD = 4 which does not
allow seamless read or write [either on the fly using A12 or
MRS]
• Bi-directional Differential Data Strobe
• Internal(self) calibration : Internal self calibration through ZQ
pin (RZQ : 240 ohm ± 1%)
• On Die Termination using ODT pin
• On-DIMM thermal sensor (Grade B)
• Average Refresh Period 7.8us at lower than TCASE 85°C,
3.9us at 85°C < TCASE < 95°C
• Asynchronous Reset
• PCB : Height 0.740” (18.75mm), double sided component
SPECIFICATIONS
CL(IDD)
Row Cycle Time (tRCmin)
Refresh to Active/Refresh
Command Time (tRFCmin)
Row Active Time (tRASmin)
Maximum Operating Power
UL Rating
Operating Temperature
Storage Temperature
9 cycles
49.5ns (min.)
260ns (min.)
36ns (min.)
5.601 W*
94 V - 0
0^o C to 85^o C
-55^o C to +100^o C
*Power will vary depending on the SDRAM and
Register/PLL used.
Continued >>
Document No. VALUERAM1257-001.A00 09/24/12 Page 1