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KVR13N9S8-4 Datasheet, PDF (1/2 Pages) List of Unclassifed Manufacturers – 4GB 1Rx8 512M x 64-Bit PC3-10600 | |||
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Memory Module Speciï¬cations
KVR13N9S8/4
4GB 1Rx8 512M x 64-Bit PC3-10600
CL9 240-Pin DIMM
DESCRIPTION
SPECIFICATIONS
This document describes ValueRAM's 512M x 64-bit (4GB)
DDR3-1333 CL9 SDRAM (Synchronous DRAM), 1Rx8 memory
module, based on eight 512M x 8-bit DDR3-1333 FBGA compo-
nents. The SPD is programmed to JEDEC standard latency
DDR3-1333 timing of 9-9-9 at 1.5V. This 240-pin DIMM uses
gold contact fingers. The electrical and mechanical specifica-
tions are as follows:
FEATURES
CL(IDD)
Row Cycle Time (tRCmin)
Refresh to Active/Refresh
Command Time (tRFCmin)
Row Active Time (tRASmin)
Maximum Operating Power
UL Rating
Operating Temperature
Storage Temperature
9 cycles
49.125ns (min.)
260ns (min.)
36ns (min.)
TBD W*
94 V - 0
0o C to 85o C
-55o C to +100o C
⢠JEDEC standard 1.5V (1.425V ~1.575V) Power Supply
⢠VDDQ = 1.5V (1.425V ~ 1.575V)
*Power will vary depending on the SDRAM used.
⢠667MHz fCK for 1333Mb/sec/pin
⢠8 independent internal bank
⢠Programmable CAS Latency: 9, 8, 7, 6
⢠Programmable Additive Latency: 0, CL - 2, or CL - 1 clock
⢠Programmable CAS Write Latency(CWL) = 7 (DDR3-1333)
⢠8-bit pre-fetch
⢠Burst Length: 8 (Interleave without any limit, sequential with
starting address â000â only), 4 with tCCD = 4 which does not
allow seamless read or write [either on the fly using A12 or
MRS]
⢠Bi-directional Differential Data Strobe
⢠Internal(self) calibration: Internal self calibration through ZQ
pin (RZQ : 240 ohm ± 1%)
⢠On Die Termination using ODT pin
⢠Average Refresh Period 7.8us at lower than TCASE 85°C,
3.9us at 85°C < TCASE < 95°C
⢠Asynchronous Reset
⢠PCB: Height 0.740â (18.75mm) or 1.180â (30.00mm)
Important Information: The module defined in this data sheet is one of several configurations available under
this part number. While all configurations are compatible, the DRAM combination and/or the module height
may vary from what is described here.
Continued >>
Document No. VALUERAM1241-001.C00 03/26/15 Page 1
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