IDT70T3509MS133BPI Datasheet, PDF (1/23 Pages) List of Unclassifed Manufacturers – HIGH-SPEED 2.5V 1024K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE

HIGH-SPEED 2.5V
1024K x 36
SYNCHRONOUS
IDT70T3509M
Š ^{DUAL-PORT STATIC RAM}
WITH 3.3V OR 2.5V INTERFACE
Features:
◆ _{True Dual-Port memory cells which allow simultaneous}
access of the same memory location
◆ _{High-speed data access}
– Commercial: 4.2ns (133MHz)(max.)
– Industrial: 4.2ns (133MHz)(max.)
◆ _{Selectable Pipelined or Flow-Through output mode}
◆ _{Counter enable and repeat features}
◆ _{Interrupt Flags}
◆ _{Full synchronous operation on both ports}
– 7.5ns cycle time, 133MHz operation (9.5Gbps bandwidth)
– 1.5ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 133MHz
– Fast 4.2ns clock to data out
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
◆ _{Separate byte controls for multiplexed bus and bus}
matching compatibility
◆ _{Dual Cycle Deselect (DCD) for Pipelined Output Mode}
◆ _{2.5V (±100mV) power supply for core}
◆ _{LVTTL compatible, selectable 3.3V (±150mV) or 2.5V}
(±100mV) power supply for I/Os and control signals on
each port
◆ _{Includes JTAG functionality}
◆ _{Available in a 256-pin Ball Grid Array (BGA)}
◆ _{Common BGA footprint provides design flexibility over}
seven density generations (512K to 36M-bit)
◆ _{Green parts available, see ordering information}
Functional Block Diagram
BE3L
BE3R
BE2L
BE2R
BE1L
BE1R
BE0L
BE0R
FT/PIPEL
R/WL
(2)
CE0L
CE1L
OEL
FT/PIPEL
0a 1a
1/0
a
0b 1b 0c 1c
b
c
0d 1d
d
1
0
1 /0
B B BBB B BB
W W WWW W WW
0 1 233 2 10
L L LL RRRR
Dou t0-8_ L
Dou t9-17 _L
Dou t18-2 6_L
Dou t27-3 5_L
Dout0- 8_R
Dout 9-1 7_R
Dout18-26_R
Dout27-35_R
1d 0d 1c 0c 1b 0b 1a 0a
0 /1
ab cd
1024K x 36
MEMORY
A RR AY
I/O0L - I/O35L
CLKL
A19L
A0L
REPEATL
ADSL
CNTENL
INTL
Din_L
Din_R
Counter/
Address
Reg.
CE 0 L
CE1L
R/ W L
ADDR_L
ADDR_R
INTERRUPT
LOGIC
ZZL(1)
ZZ
CONTROL
LO GI C
1d 0d
d
1c 0c
c
1b 0b
b
1a 0a
1 /0
a
1
0
1/0
FT/PIPER
R/WR
(2)
CE0R
CE1R
OER
0a 1a 0b 1b 0c 1c 0d 1d
0/1
dcba
,
FT/PIPER
C o unt er/
Address
Reg.
CE0 R
CE1R
R/ WR
ZZR(1)
I/O0R - I/O35R
A19R
CLKR
A 0R
REPEATR
ADSR
CNTENR
TDI
TDO
INTR
,
TCK
JTAG
TMS
TRST
5682 drw 01
NOTE:
1. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and OPTx
and the sleep mode pins themselves (ZZx) are not affected during sleep mode.
2. See Truth Table I for Functionality.
1
©2009 Integrated Device Technology, Inc.
JANUARY 2009
DSC 5682/8