HX316LS9IBK2-8 Datasheet, PDF (1/2 Pages) List of Unclassifed Manufacturers – CL9 204-Pin SODIMM Kit

HX318C10FB/4
HX316LS9IBK2/8
8GB (4GB 512M x 64-Bit x 2 pcs.) DDR3L-1600
CL9 204-Pin SODIMM Kit
SPECIFICATIONS
CL(IDD)
9 cycles
Row Cycle Time (tRCmin)
Refresh to Active/Refresh
Command Time (tRFCmin)
48.125ns (min.)
260ns (min.)
Row Active Time (tRASmin)
33.75ns (min.)
Maximum Operating Power
UL Rating
Operating Temperature
Storage Temperature
TBD W* @1.35V
94 V - 0
0^o C to 85^o C
-55^o C to +100^o C
*Power will vary depending on the SDRAM used.
DESCRIPTION
HyperX HX316LS9IBK2/8 is a kit of two 512M x 64-bit (4GB)
DDR3L-1600 CL9 SDRAM (Synchronous DRAM) 1Rx8, low
voltage, memory modules, based on eight 512M x 8-bit DDR3
FBGA components per module. Total kit capacity is 8GB. Each
module kit has been tested to run at DDR3L-1600 at a low
latency timing of 9-9-9 at 1.35V or 1.5V. Additional timing
parameters are shown in the PnP Timing Parameters section
below. The JEDEC standard electrical and mechanical specifi-
cations are as follows:
Note: The PnP feature offers a range of speed and timing options to support
the widest variety of processors and chipsets. Your maximum speed will
be determined by your BIOS.
PnP JEDEC TIMING PARAMETERS:
• DDR3-1600 CL9-9-9 @1.35V or 1.5V
• DDR3-1333 CL8-8-8 @1.35V or 1.5V
• DDR3-1066 CL6-6-6 @1.35V or 1.5V
FEATURES
• JEDEC standard 1.35V (1.28V ~ 1.45V) and 1.5V (1.425V ~
1.575V) Power Supply
• VDDQ = 1.35V (1.28V ~ 1.45V) and 1.5V (1.425V ~ 1.575V)
• 800MHz fCK for 1600Mb/sec/pin
• 8 independent internal bank
• Programmable CAS Latency: 11, 10, 9, 8, 7, 6
• Programmable Additive Latency: 0, CL - 2, or CL - 1 clock
• 8-bit pre-fetch
• Burst Length: 8 (Interleave without any limit, sequential with
starting address “000” only), 4 with tCCD = 4 which does not
allow seamless read or write [either on the fly using A12 or
MRS]
• Bi-directional Differential Data Strobe
• Internal(self) calibration : Internal self calibration through ZQ
pin (RZQ : 240 ohm ± 1%)
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower than TCASE 85°C,
3.9us at 85°C < TCASE < 95°C
• Asynchronous Reset
• PCB : Height 1.180” (30.00mm), double sided component
Continued >>
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Document No. 4807047-001.A00 05/20/14 Page 1