HJV Datasheet, PDF (1/1 Pages) List of Unclassifed Manufacturers – Complementary Bipolar Process

HJV
Complementary Bipolar Process
Data Sheet DS00107 / June 2010
HJV is a high voltage version of the RF- HJ double polysilicon trench
isolated complementary bipolar process, optimized for very high linearity
applications.
Key parameters (minimum geometry device)
NPN
PNP
fT
9 GHz 8GHz
(Ic=0.1mA, Vce=2V)
CJC
2 fF
4 fF
CJE
5fF
4.2fF
Bvceo
> 12V
>12V
Applications
• Very high linearity applications
• High Speed amplifiers
npn parameters (0.6 x 4.0um emitter)
parameter Condition
Value
fT
Ic=0.2mA Vce=2V 8.5
HFE
Ic=10μA Vcb=0
170
VAF
115
BVCEO Ic=1μA
>12
BVCBO Ic=1μA
>31
CJE
Vbe=0
14
CJC
Vbc=0
5.5
CJS
Vcs=0
15
Units
GHz
V
V
V
fF
fF
fF
Key Process Feature
• Varactor diodes - 0.45 fF/μm²
• Polysilicon resistors -110/155/1400 Ohms/sq
• Schottky Diodes V_f=0.5 V
• MIM capacitors - 0.5 fF/μm² (optional)
• MIS capacitors - 1.0 fF/μm² (optional)
• Two level or three level metal option
Npn cross section
Base
Oxide
Emitter
Collector
oxide
P+ _base
P+
epitaxy (n-)
DC
BN
CS
CS
Substrate (p-)
Vertical pnp parameters (0.6 X 4.0μm emitter)
parameter Condition
Value Units
fT
Ic=0.2mA Vce=2V 8
GHz
HFE
Ic=1μA Vcb=0
55
VAF
50
V
BVCEO Ic=1μA
>12
V
BVCBO Ic=1μA
>25
V
CJE
Vbe=0
12
fF
CJC
Vbc=0
5.5
fF
CJS*
Vcs=0
50
fF
Polysilicon Resistor Values
parameter Value
LoP
155 ± 20
LoN
110 ± 20
HiP
1.4 ± 0.2
Units
Ω
Ω
kΩ
Vpnp cross section
Base Emitter
Collector
Well
N+
N+
Base
pwell
DC
Oxide _OOxixdidee
BP
BSUB
CS
oxide ^Oxide
Substrate (p-)
CS
Design Rules
Feature
Emitter
LoP, LoN resistor
HiP resistor
Contact
1st Layer metal
2^nd layer metal
3^rd layer metal
Min μm
0.6 X 1.6
1.2
1.0
1.0 X 1.6
1.4
1.4
3.0
Spacing μm
0.8
0.8
1.4
1.0
1.0
2.0
Data Sheet DS00107 / June 2010
Process information and data (“Information”) in this document is an outline only , for general information purposes ; it does not constitute a representation or
warranty as to capability , performance or suitability of the Process for any given application. User must satisfy himself that the Process is suitable for his
requirements .
While Information herein is believed correct and accurate , it is subject to change without notice and Plessey accepts no liability arising from the use or application of
such Information.
All use of , and product manufactured and supplied using the Process , will be subject to Plessey’s standard trading terms, which are available on request .
Plessey Semiconductors Ltd. Tamerton Road, Roborough, Plymouth, United Kingdom, PL6 7BQ
Tel: [phone]
Fax: [phone]
Web: www.plesseysemiconductors.com