DTM64360B Datasheet, PDF (1/13 Pages) List of Unclassifed Manufacturers – 2GB - 240-Pin 1Rx8 Registered ECC DDR3 DIMM

DTM64360B
2GB - 240-Pin 1Rx8 Registered ECC DDR3 DIMM
Features
240-pin JEDEC-compliant DIMM, 133.35 mm wide by 30 mm
high
Operating Voltage: 1.5V ± 0.075
I/O Type: SSTL_15
On-board I2C temperature sensor with integrated serial
presence-detect (SPD) EEPROM.
Data Transfer Rate: 10.6 Gigabytes/sec
Data Bursts: 8 and burst chop 4 mode
ZQ Calibration for Output Driver and On-Die Termination (ODT)
Programmable ODT / Dynamic ODT during Writes
Programmable CAS Latency: 6, 7, 8, and 9
Description
Identification
DTM64360B 256Mx72
2GB 1Rx8 PC3-10600R-9-11-A0
Performance range
Clock / Module Speed / CL-tRCD -tRP
667 MHz / PC3-10600 / 9-9-9
533 MHz / PC3-8500 / 8-8-8
533 MHz / PC3-8500 / 7-7-7
400 MHz / PC3-6400 / 6-6-6
DTM64360B is a registered 256Mx72 memory module,
which conforms to JEDEC's DDR3, PC3-10600
standard. The assembly is a Single-Rank. The Rank is
comprised of nine 256Mx8 DDR3-1333 Hynix SDRAMs.
One 2K-bit EEPROM is used for Serial Presence
Detect and a combination register/PLL, with Address
and Command Parity, is also used.
Both output driver strength and input termination
impedance are programmable to maintain signal
integrity on the I/O signals in a Fly-by topology.
A thermal sensor accurately monitors the DIMM module
and can prevent exceeding the maximum operating
temperature of 95C.
Bi-Directional Differential Data Strobe signals
SDRAM Addressing (Row/Col/Bank): 15/10/3
Fully RoHS Compliant
Pin Configuration
Pin Description
Front Side
Back Side
Name
Function
1 VREFDQ 31 DQ25
2 VSS 32 VSS
3 DQ0 33 /DQS3
4 DQ1 34 DQS3
5 VSS 35 VSS
6 /DQS0 36 DQ26
7 DQS0 37 DQ27
8 VSS 38 VSS
9 DQ2 39 CB0
10 DQ3 40 CB1
11 VSS 41 VSS
12 DQ8 42 /DQS8
13 DQ9 43 DQS8
14 VSS 44 VSS
15 /DQS1 45 CB2
16 DQS1 46 CB3
17 VSS 47 VSS
18 DQ10 48 VTT
19 DQ11 49 VTT
20 VSS 50 CKE0
21 DQ16 51 VDD
22 DQ17 52 BA2
23 VSS 53 /ERR_OUT
24 /DQS2 54 VDD
25 DQS2 55 A11
26 VSS 56 A7
27 DQ18 57 VDD
28 DQ19 58 A5
29 VSS 59 A4
30 DQ24 60 VDD
** Not used
61 A2
62 VDD
63 CK1**
64 /CK1**
65 VDD
66 VDD
67 VREFCA
68 PAR_IN
69 VDD
70 A10/AP
71 BA0
72 VDD
73 /WE
74 /CAS
75 VDD
76 /S1**
77 _ODT1**
78 VDD
79 /S2, NC**
80 VSS
81 DQ32
82 DQ33
83 VSS
84 /DQS4
85 DQS4
86 VSS
87 DQ34
88 DQ35
89 VSS
90 DQ40
91 DQ41 121 VSS
151 VSS
181 A1
211 VSS
CB[7:0]
Data Check Bits
92 VSS 122 DQ4
93 /DQS5 123 DQ5
152 DM3
153 /TDQS12
94 DQS5 124 VSS
154 VSS
95 VSS 125 DM0 155 DQ30
96 DQ42 126 /TDQS9 156 DQ31
97 DQ43 127 VSS
98 VSS 128 DQ6
99 DQ48 129 DQ7
157 VSS
158 CB4
159 CB5
100 DQ49 130 VSS
101 VSS 131 DQ12
102 /DQS6 132 DQ13
160 VSS
161 DM8
162 /TDQS17
182 VDD
183 VDD
184 CK0
185 /CK0
186 VDD
187 /EVENT
188 A0
189 VDD
190 BA1
191 VDD
192 /RAS
212 DM5
DQ[63:0]
Data Bits
213 /TDQS14 DQS[8:0], /DQS[8:0] Differential Data Strobes
214 VSS
215 DQ46
DM[8:0]
/TDQS[17:9]
Data Mask
Termination strobes
216 DQ47 CK[1:0], /CK[1:0] Differential Clock Inputs
217 VSS
218 DQ52
CKE[1:0]
/CAS
Clock Enables
Column Address Strobe
219 DQ53 /RAS
Row Address Strobe
220 VSS
221 DM6
/S[3:0]
/WE
Chip Selects
Write Enable
222 /TDQS15 A[15:0]
Address Inputs
103 DQS6 133 VSS
163 VSS
104 VSS 134 DM1 164 CB6
105 DQ50 135 /TDQS10 165 CB7
193 /S0
194 VDD
195 ODT0
223 VSS
224 DQ54
225 DQ55
BA[2:0]
ODT[1:0]
SA[2:0]
Bank Addresses
On Die Termination Inputs
SPD Address
106 DQ51 136 VSS
166 VSS
196 A13
226 VSS
SCL
SPD Clock Input
107 VSS 137 DQ14 167 NC (TEST) 197 VDD
227 DQ60 SDA
SPD Data Input/Output
108 DQ56 138 DQ15 168 /RESET 198 /S3, NC** 228 DQ61 /EVENT
Temperature Sensing
109 DQ57 139 VSS
169 _CKE1** 199 VSS
229 VSS
/RESET
Reset for register and DRAMs
110 VSS 140 DQ20
111 /DQS7 141 DQ21
170 VDD
171 A15
200 DQ36
201 DQ37
230 DM7
PAR_IN
231 /TDQS16 /ERR_OUT
Parity bit for Addr/Ctrl
Error bit for Parity Error
112 DQS7 142 VSS
172 A14
113 VSS 143 DM2 173 VDD
114 DQ58 144 /TDQS11 174 A12/BC
115 DQ59 145 VSS
116 VSS 146 DQ22
117 SA0 147 DQ23
175 A9
176 VDD
177 A8
118 SCL
119 SA2
120 VTT
148 VSS
149 DQ28
150 DQ29
178 A6
179 VDD
180 A3
202 VSS
203 DM4
232 VSS
233 DQ62
204 /TDQS13 234 DQ63
205 VSS
206 DQ38
207 DQ39
235 VSS
236 VDDSPD
237 SA1
208 VSS
209 DQ44
210 DQ45
238 SDA
239 VSS
240 VTT
A12/BC
A10/AP
VSS
VDD
VDDSPD
VREFDQ
VREFCA
VTT
NC
Combination input: Addr12/Burst Chop
Combination input: Addr10/Auto-precharge
Ground
Power
SPD EEPROM Power
Reference Voltage for DQ’s
Reference Voltage for CA
Termination Voltage
No Connection
Document 06943, Revision A, 3-Oct-11 Dataram Corporation  2011
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