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78A2GC8AF00C Datasheet, PDF (1/7 Pages) List of Unclassifed Manufacturers – 2GB DDR3 SDRAM SODIMM with SPD | |||
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Apacer Memory Product Specification
2GB DDR3 SDRAM SODIMM with SPD
Ordering Information
Part Number Bandwidth Speed Grade Max Frequency
78.A2GC8.AF00C 8.5GB/sec 1066Mbps
533MHz
CAS Latency
CL7
Density
Organization
Component
Composition
Number of
Rank
2GB 256Mx64 256Mx8*8EA
1
Specifications
⢠On Dimm Thermal Sensor: No
⢠Density: 2GB
⢠Organization
 256M words à 64 bits, 1 rank
⢠Mounting 8 pieces of 2G bits DDR3 SDRAM sealed
in FBGA
⢠Package: 204-pin socket type small outline dual in
line memory module (SO-DIMM)
 PCB height: 30.0mm
 Lead pitch: 0.6mm (pin)
 Lead-free (RoHS compliant)
⢠Power supply: VDD = 1.5V ± 0.075V
⢠Eight internal banks for concurrent operation
(components)
⢠Interface: SSTL_15
⢠Burst lengths (BL): 8 and 4 with Burst Chop (BC)
⢠/CAS Latency (CL): 6, 7, 8, 9
⢠/CAS write latency (CWL): 5, 6, 7
⢠Precharge: auto precharge option for each burst
access
⢠Refresh: auto-refresh, self-refresh
⢠Refresh cycles
 Average refresh period
7.8µs at 0°C ⤠TC ⤠+85°C
3.9µs at +85°C < TC ⤠+95°C
⢠Operating case temperature range
 TC = 0°C to +95°C
Features
⢠Double-data-rate architecture; two data transfers per
clock cycle
⢠The high-speed data transfer is realized by the 8 bits
prefetch pipelined architecture
⢠Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
⢠DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
⢠Differential clock inputs (CK and /CK)
⢠DLL aligns DQ and DQS transitions with CK
transitions
⢠Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
⢠Data mask (DM) for write data
⢠Posted /CAS by programmable additive latency for
better command and data bus efficiency
⢠On-Die-Termination (ODT) for better signal quality
 Synchronous ODT
 Dynamic ODT
 Asynchronous ODT
⢠Multi Purpose Register (MPR) for temperature read
out
⢠ZQ calibration for DQ drive and ODT
⢠Programmable Partial Array Self-Refresh (PASR)
⢠/RESET pin for Power-up sequence and reset
function
⢠SRT range:
 Normal/extended
 Auto/manual self-refresh
⢠Programmable Output driver impedance control
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